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Issue 1, 2012
Do Standards Matter to Users? You Bet!
In the previous issue of Insight, we talked about why standards matter to Synopsys and explained how Synopsys collaborates with industry partners as well as leads by example in standards activities. In this article, we will examine the need for users to participate in standards activities.
Defining the User
Before we address the ‘why’ question – that is, the reasons for users to participate in standardization activities – it is important to know how we define a user in the context of standards. The definition depends on the context of how the standard is used. Limiting the scope of our definitions to just the EDA standards, such as SystemVerilog, it becomes easy to define a user. Even though each user’s perspective might be slightly different, the user community of EDA standards is very broad. An EDA tool developer is a user of the SystemVerilog standard when they implement the standard in a tool, such as a simulator from the specification like IEEE 1800. An IP supplier is a user of the SystemVerilog standard as they create a design written in SystemVerilog by referring to the same standard. A chip designer – often a common reference to ‘user’ – is also a user as they write verification environment in SystemVerilog. Similar examples exist among users of other standards, such as library models (Liberty from IEEE-ISTO LTAB and Accellera’s UVM). So, if everyone is using the same standard, why does a standard matter to the user?
The Standards Developer
First, let’s talk about the users who are very interested in creating a standard. If you are a leading edge tool, IP, design or verification developer, you are always at the edge of the current methodologies. You are always seeking new ways to go beyond the current limits. In fact, you are the one who is breaking the current methodologies searching for solutions to larger challenges. And in that quest, you are looking for collaboration with other members of the user community – chip designers, tool developers and IP suppliers. You want to be proactive in defining methodologies that will solve your most difficult problems. This requires exchanging information among collaborating parties which in turn requires well defined interfaces based on standards. That is why you – a user – are participating in the standards development activity. The key phrase here is “standards development” or standardization activity. Of course, you will then implement that standard in the form of a tool, an IP or a description of your chip to validate the methodology as a solution to the larger problem. So the standard you helped develop is a vehicle to achieve your end goal or solution.
Using Standards to Solve Problems
Now, let’s look at the situation a little differently; if you are not a leader then you are a follower (yikes!). That is not meant as an insult to anyone. You may be a leader in defining a communication protocol standard who may not require change in SystemVerilog to describe the design or how to verify it. That is why we have to define the context standards users.
You may be facing the same problems addressed by the leaders a few years ago in their previous projects. This means the tools, IPs and methodologies are already defined in the industry and you are adopting a well-established flow. Some users may call it a risk-free approach. You may not be excited about developing a new standard or have the resources to participate in a potentially lengthy process. However, as a savvy user, you care about ensuring the long-term success of your investment into design and verification tools, IPs you purchased, as well as the skills your team members have developed. You want to be able to augment your existing tool set when your challenges grow as a result of design complexity and migration to advanced process node. You want your design environment to ‘live on’ for a long time, customizing it as needed and not having to retrain your engineers every year or for every new project. You want to be able to hire bright engineers from the industry or from universities and have them contribute immediately to your design project. This is possible if you are using standards-based IPs and tools and your design and verification environment are based on standards.
When referencing standards, it is important to note the use of the plural form of the word – standards. By doing so, we recognize that there are many standards playing important roles in the entire design flow as the design data marches its journey from concept to silicon. At various stages of implementation and verification, the design needs to be represented in many different forms such as functionality, test cases and assertions, timing budget, power intent, defect test structures, library cells, process design rules, manufacturing directives, etc. Most of these representations require an appropriate standard format as input to a tool. Some tools also generate modified design data in a standard format (e.g. netlist or GDSII). Standards also provide the necessary glue between the tools in the design flow. As a designer, you must care about the support of respective standards by your design tools at each stage in the design flow. If your design flow leaves some questions unanswered, it is time to look at the standard and see if additional, different, or better data must be exchanged at various stages by enhancing the standard. There is your opportunity to lead the standards development!
As an end-user, you care about making sure that your design data or verification environment will work with multiple tools; as an IP developer, you care about integrating your IP in customer’s design environments; as a tool developer, you care about having enough designs and IPs that your tools can be used with. Thus, the standard brings together the mutual interest of the user community, whether you were one of the leaders to develop the standard or not!
- Time to Participate!
If you are a user – in the broadest sense we defined earlier – what should you do about your vested interest in the standards activities? As the old adage goes, “You can’t win from the sidelines; You must get out and play.” In our case of standards and standardization activities, there are several ways to get involved:
- Educate yourself on relevant standards. In particular, you should be familiar with IEEE Design Automation standards and Accellera standards. If you are a chip designer or an IP developer, you should also be familiar with various ‘application’ standards such as interconnects and communication protocols.
- Become a member of these standards groups. Membership may be individual or for the company. Benefits typically include discounted access to approved standards, early access to draft standards, and the ability to participate in the ballot process as well as in the working group to develop the standard.
- Be an active user of standards in your work. You know the benefits!
- Participate in the standards development effort. Make an impact beyond your project in advancing technology for the entire industry. Be a leader!
Synopsys has been playing the standards game since its inception and continues to evolve its support for and development of standards and standards-based interoperability to help users focus on innovation. Hope to meet you at the next Standards Game. Let’s play.
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About the Author
Yatin Trivedi is the director of Standards and Interoperability Programs at Synopsys. He represents Synopsys on the Standards Board and the Standards Education Committee (SEC) of the IEEE Standards Association (IEEE-SA), the Education Activities Board (EAB) of IEEE, the Board of Directors of IEEE Industry Standards and Technology Organization (IEEE-ISTO), and the Board of Directors of Accellera. He is Editor-in-Chief of the Standards Education Committee eZine, vice chair of Design Automation Standards Committee (DASC), and member of IEEE-SA's NesCom and AudCom governance committees. He manages interoperability initiatives as part of the corporate marketing strategic alliances group and works closely with the Synopsys University program.