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Issue 3, 2011

Technology Update
Overcoming Cost and Complexity in Verification

David Park, director of marketing for the System-to-Silicon Verification Solution at Synopsys, looks at the cost and complexity involved in verification today, and explains how verification teams can overcome the technical challenges.

It's plain to see why verification has become an enormous challenge. First, there's the growth in complexity. Consumers are demanding greater functionality and performance from smartphones and other devices, so designers must create faster, more sophisticated ICs and SoCs, often containing more than 100m gates, incorporating mixed-signal content and increasing blocks of third-party IP.

It's no longer possible to justify the cost special-purpose ASICs for every application. Instead, product companies are increasingly turning to application-specific standard products (ASSPs), and using them in multiple product derivatives. As a result, designers must consider a host of different functions and capabilities that may need to be accomplished in silicon and enabled through software.

Software development is becoming increasingly important and costly for SoC designs, representing up to 70% of overall R&D expenses at the 22-nanometer (nm) process node. It has also become much more time-consuming to bring new products to market. In order to be competitive, it is necessary to begin integrating hardware and software, and begin debugging, earlier in the design cycle.

Other factors that drive the cost of verification include algorithmic verification, the desire to reduce cost and power by optimizing the system architecture, block-level verification and formal hybrid verification.

All of these challenges make it harder than ever to know when verification is "finished". As a result, it's taking verification teams much longer to find the last few bugs in their designs.

The Challenges of Complexity
Today's complex SoCs present design teams with a broad range of technical challenges, making verification both a complex and open-ended process. One challenge at the system level is the algorithmic verification of functions such as video or image processing. Verification of complex power management schemes adds even greater levels of complexity to the verification process. And, of course, verification teams must perform full-chip regression testing, block-level verification, and power management validation – which is no longer confined to portable electronic designs.

Mixed-signal content creates the need to perform cell characterization as well as block- and system-level circuit simulation and analysis. The need to verify, at different levels of abstraction, a combination of external IP, which almost all chips incorporate to some level, and internal IP, makes the process even more complex.

Finally, the design team needs to validate the system, and integrate and test software as early as possible. Faster product lifecycles and tighter time-to-market windows mean that waiting for working silicon is no longer an option. It is now too expensive to make corrections if the team finds major hardware-software issues during system validation.

Overcoming Verification Challenges
How can verification teams overcome these challenges? The Synopsys System-to-Silicon (S2S) Verification Solution provides a set of technologies, proven methodologies and IP, along with critical links and support for industry standards. It enables design teams to verify their designs quickly and easily, improve the quality of the most complex designs, and to achieve first-pass silicon success.

This solution makes use of the industry's broadest and deepest offering of products, covering everything from algorithmic simulation and virtual prototyping to simulation and formal verification, as well as high-performance and precision analog simulation (Figure 1).

Figure 1. Synopsys System-to-Silicon (S2S) Verification Solution
Figure 1: Synopsys System-to-Silicon (S2S) Verification Solution

Functional Verification
Synopsys built VCS® from the ground up for high-performance verification of RTL-based designs. To help find design bugs even earlier, it now includes multi-core technology that cuts verification time (by 200% to 700%) by running design, testbench, and assertions in parallel on machines with multiple cores. In addition to greater speed, VCS provides a Verification Planner, which helps drive verification from specification to closure.

After simulation, VCS also provides powerful analysis capabilities, including a global coverage database that allows users to perform unified queries as well as unified report generation. Coverage metrics allow users to see where they are relative to their coverage goals. VCS also offers automatic convergence technology that dramatically reduces the time it takes to reach full functional coverage.

To connect to the system level, VCS offers SystemVerilog and SystemC transaction-level model (TLM) adapters for easier integration of TLM components into designs, and includes transaction-level debugging capabilities.

System-Level Verification
Synopsys has invested in the industry's broadest system-level verification portfolio, which provides support for:
  • Block creation, integration and reuse
  • Architecture optimization
  • Software virtual prototyping for early software development
  • FPGA-based prototyping for system integration, system validation and early software development

We have recently acquired a number of industry-leading verification technology providers, and now rank as the industry leader in FPGA design and virtual prototyping, and algorithmic design. We have also enhanced our verification technology portfolio with capabilities in architectural design, processor design, and C/C++ high-level synthesis.

All of our system-level design and verification tools provide linkages to traditional functional verification technologies. This allows design teams to make the most of all aspects of their system-level environment back to the functional domain, as well as silicon implementation, either as an ASIC, ASSP, or FPGA.

Mixed-Signal Verification
In the mixed-signal domain, the overwhelming number of simulations that designers need to run has negatively impacted their productivity. Combined with extracted post-layout parasitics, these now far exceed the capacity of traditional simulation solutions.

Synopsys' CustomSim™, the most widely deployed FastSPICE solution, addresses this challenge, unifying Synopsys circuit simulation technologies to deliver superior verification performance and capacity for all design types, including custom digital, memory, and analog/mixed-signal.

To provide the highest throughput for mixed-signal simulation, CustomSim is tightly coupled with VCS through a direct-kernel interface. A flexible usage model further allows for any mixture of extraction and design hierarchy, with full language support for all major verification languages.

The Synopsys System-to-Silicon Verification Solution also includes the industry's most advanced analog debugging and visualization environment. The most recent release of CustomSim has been enhanced with a comprehensive transistor-level debugging environment for analog, mixed-signal and SoC designs, and even higher performance and capacity – up to 22 times faster, depending on the design type.

Verification Methodology
Since Synopsys published the Verification Methodology Manual (VMM) for SystemVerilog in 2005, we have continued to invest in verification methodologies and expanded our offering to include register and hardware abstraction layers, VMM for low power, and TLM 2.0 support. We are continuing to expand our methodologies with support for analog/mixed signal, OVM, UVM and we have also recently published a new FPGA-based prototyping methodology manual (FPMM).

Verification IP
We offer the broadest range of IP in the industry – analog IP, interface IP, IP for RTL, IP for system-level design with virtual prototyping applications, as well as models for use with HAPS, the Synopsys FPGA-based virtual prototyping solution.

Critical Links
A key capability of the Synopsys System-to-Silicon Verification Solution is the ability to perform multi-level, mixed-domain verification. In addition to being able to provide high-performance simulation links between VCS and CustomSim, our solution provides similar links between almost every product in our verification portfolio.

Support for Industry Standards
We have a heritage of embracing industry standards, as evidenced by our support for SystemC, System Verilog, UPF, UVM, and many others. We also work closely with the IEEE and Accellera to provide support for new and emerging industry standards.

Performance, Capacity and Accuracy
The Synopsys System-to-Silicon Verification Solution delivers what designers need for a new era of complexity – performance, capacity, and accuracy. Furthermore, it solves the most critical dilemma facing electronics makers today – how to begin developing software for a chip and using software to determine how a chip performs in the real world before the chip actually exists. Whether it is silicon virtual prototyping, high-performance functional verification of RTL-based designs, or the industry's leading FPGA prototyping tools, we offer the broadest range of best-in-class technologies. This combination delivers a complete verification solution – from the system level to RTL – that enables design and verification teams to get a handle on skyrocketing verification costs and bring compelling products to market faster than ever.

About the Author

David Park
As the director of Solutions Marketing at Synopsys, Inc., David Park is currently responsible for Synopsys' System-to-Silicon verification solution, a comprehensive approach to design verification that includes virtual prototyping, electro-mechanical analysis, FPGA-based prototyping and functional and analog verification. Prior to joining Synopsys, Park held positions in the areas of corporate strategy, marketing and engineering at Cadence, C Level Design, Mentor Graphics and Rockwell International. Most recently, he served as group director of the Corporate Strategy Group at Cadence Design Systems responsible for market segmentation and analysis, and at C Level Design as the vice-president of marketing. Park has a BSEE from the University of California, Irvine.

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