Synopsys Innovation Update 

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Issue 1, 2012

Synopsys Innovation Update
Latest News on Product Updates, Technologies, Services and Solutions

Synopsys offers a wide range of products, solutions, and services to the global electronics market for designing and manufacturing semiconductors. In this article, we provide a brief overview of key additions to some of our existing solutions as well as showcase recent innovations to Synopsys’ ever-growing lineup of software, IP and services.

Figure 1
Figure 1: The Synopsys product portfolio spans from Systems to SoC to Silicon

System Design
The Identify RTL debugger allows users to instrument RTL HDL and then, while remaining at the RT-Level, debug the implemented FPGA on live, running hardware. Identify provides flexible trigger expressions to help the designer isolate system states and provides a high degree of visibility inside the FPGA to improve debug efficiency. The latest release of Identify RTL debugger includes HAPS Deep Trace Debug (DTD), which expands signal visibility and sample memory capacity by 100X with Synopsys HAPS systems.
Learn more about Identify.
Certify is the leading multi-FPGA ASIC prototyping software tool for ASIC designers who use FPGA-based prototypes for software development, hardware/software integration, and system validation. Certify allows users to automate the migration of ASIC RTL and Synopsys DesignWare IP to the hardware resources of the prototyping PCB platform comprised of multiple FPGAs and other ICs. The Certify tool works seamlessly with Synopsys HAPS systems for multi-board management and automatically produces HAPS-specific pin-sharing IP for multi-MHz FPGA-to-FPGA transmission performance. By producing accurate static timing and resource analysis of multi-FPGA designs, Certify algorithms help maximize the clock performance and data throughput of an FPGA-based prototype.
Learn more about Certify.
Discovery™ VIP
Discovery™ VIP
Synopsys Verification IP (VIP) provides the components and features needed by verification engineers to verify their SoC protocols and interfaces. The VIP portfolio includes AMBA, USB, OCP, MIPI and ready-made verification suites for many other difficult-to-design protocols. The new Discovery VIP product line is implemented entirely in SystemVerilog utilizing native UVM, VMM, or OVM methodologies. Discovery VIP is geared to focus on the following key areas: rapid configuration and test, high performance, easier debug, and quick coverage closure. Enhancements made to these four targeted areas will greatly improve overall verification productivity.
Read the full article about Discovery VIP in this issue of Insight.
Learn more about Verification IP.
DesignWare IP
DesignWare® Duet Packages
DesignWare® Duet Packages
DesignWare Embedded Memories and Logic Libraries have provided designers with the IP necessary to meet their SoC designs. Synopsys now offers the DesignWare Duet Packages, giving designers the best combination of memory compilers, logic libraries and integrated memory test and repair to meet their specifications for performance, power and area. This package contains all of the IP elements designers need to successfully complete their SoC designs.
Learn more about DesignWare Duet Packages.
CATS is a highly scalable and flexible software application that transcribes complex design data into machine readable instructions for e-beam and laser machines. Delivering superior slicing quality, uniformity, symmetry, and advanced sliver control, CATS’ advanced fracture engine offers unmatched quality. The latest version of CATS (E-2011.03-SP6) provides improvements to the tool, including reduced VSB12 Direct Output file sizes and enhancements to the DQM job list and description. Synopsys customers can access their SolvNet account to view the full release notes as well as download instructions.
Learn more about CATS.

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