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Issue 2, 2012

Standards Column
Peace, Love and Interoperability in the EDA Standards World!

For the long-time EDA historians, EDA Standards have meant war, not peace!

Today’s system-on-chip (SoC) flow and its predecessors dating back to the early 1980s are inherently based on EDA standards for an obvious reason: the semiconductor ecosystem is quite complex. There are at least a dozen or more major steps where design is successively refined from concept to silicon. The handoff at each stage requires a well-defined standard – a format, a language, an API, etc. - so that there is sufficient bidirectional communication between the predecessor and the successor stages. For example, GDSII has served the industry for well over 30 years in “taping out” designs from engineering teams to manufacturing teams.

Establishing a language, a format or a methodology as a standard across the industry can separate a product, or even a company, between success and failure. We have seen several contentious issues in the past decade: SystemVerilog, Low Power, Verification methodology, and Analog PDKs, just to name a few. However, in the past two years, the EDA community, users as well as vendors, have been heading in the direction of unprecedented collaboration that has yielded some exceptionally good results.

Here are a few observations:

Nearly a decade ago, the industry was evenly split on Verilog vs. VHDL. Verilog was “winning” due to its broad appeal to designers who were learning the “simpler language” to implement complex logic (functionality) described in RTL with Synopsys Design Compiler®. However, Verilog’s ability to write complex testbenches was limited, and there were multiple competing efforts at that time to extend the language and its implementation (simulator) to create more powerful ways to test the designs. Notably, Vera and ‘e’ were creating language based co-simulation environments, whereas Superlog was creating a new language encompassing Verilog. Those competing efforts, with many good ideas but limited appeal to broad markets, paved the way for the industry to recognize the need for a more powerful hardware design and verification language. Several leading users and vendors, initially under Accellera and later under IEEE, created SystemVerilog (IEEE Std. 1800) between 2002 and 2005. The original technical contribution to Accellera was made by Synopsys. By 2008, SystemVerilog had become the de facto standard in the industry. With the proliferation of SystemVerilog, and its predecessor Verilog, the third-party design IP (“synthesizable cores” as it was called for several years) industry moved from being a cottage industry into its own recognized, mainstream segment working closely with the EDA industry. The emergence of the IP industry was as much due to the need for reuse-based methodologies as it was to the availability of a stable, single language providing the development and delivery platform.

The success of SystemVerilog led to the creation of object-oriented verification methodologies – some structured and some ad-hoc. Similar to design IPs, several entrepreneurs were building verification IPs (VIPs) for testing compliance with well-defined (standard) bus and communication protocols, such as SATA, USB and PCI. Eventually, two similar but incompatible methodologies emerged: VMM and OVM. It became apparent that in order to build reusable verification environments for increasingly complex SoCs, there must be a way to interoperate testbenches built on top of VMM and OVM base classes. Between 2009 and 2011, Universal Verification Methodology (UVM) emerged from Accellera. Today, it is widely supported by all EDA vendors and is being adopted by most new SoC projects. Several collaborative tutorials and workshops have been conducted at DAC, DVCon and various other venues in the past two years, clearly indicating there is no significant discord on this topic in the industry.

Let’s turn our attention from SoC implementation and verification to system-level design and verification. After initial skepticism of an Open Source effort to define a language for system design, the Open SystemC Initiative (OSCI) brought together a large group of system architects (modelers) and tool developers to focus on SystemC based on the donation from Synopsys and CoWare (an independent company prior to being acquired by Synopsys in 2010). A decade-long crusade has successfully standardized SystemC language (IEEE Std. 1666-2011), Transaction Level Modeling library (TLM-2.0, part of IEEE Std), and a proof-of-concept reference simulator that runs on a wide range of hardware platforms and operating systems. Evident from the attendance at Worldwide SystemC User Groups (SCUGs) as well as the quality and variety of papers presented, one could easily observe that the system design and verification community has been busy developing and adopting system modeling and verification methodology built on top of the SystemC standard.

Figure 1

In fact, this rapid evolution and adoption of the SystemVerilog and SystemC standards and broad interest in aligning the respective methodologies has brought many experts to realize the need for coordinating adjacent activities. Two recent standards organization mergers are an indication of how the industry consortia continue to evolve in response to these changes:
  • The SPIRIT Consortium and Accellera merged in 2009, bringing increased participation in IP-XACT (IEEE Std. 1685) in close cooperation with all the EDA standards from Accellera. One of the enhancements will bring greater consistency in register modeling across SoC designers and IP developers.
  • OSCI and Accellera merged in 2011, forming Accellera Systems Initiative. The new organization is already exploring the alignment of verification methodologies based on SystemC and SystemVerilog, and analog mixed-signal (AMS) extensions to these languages.
  • Continuing evolution of the operational alignments - policies, procedures, IP rights, etc. - of the new organization is also creating opportunity for unprecedented collaboration with other standards development organizations (SDOs) such as IEEE. For example, Accellera has renewed its commitment to make certain IEEE standards available at no cost to the industry.

Here is one last example to show that harmony keeps growing in the standards world. Those familiar with the low-power format standardization will recall two competing efforts about seven years ago. Today, there is no longer a debate of the right or wrong way, winners or losers. There is really only one way, and that is IEEE 1801. After all, both efforts were attempting to help describe the low-power intent for design and verification. Suffice to say, common sense has prevailed, and now the work is within IEEE 1801. All the EDA vendors who provide low-power solutions are sitting at the table with all the leading low-power chip designers to address issues in managing power for the next generation SoCs. At a recent 1801 working group meeting, there were at least 20 participants representing EDA, IP, SoC and Systems communities.

Of course, before we declare panacea or euphoria, we should acknowledge that more work needs to be done in the standards area as technology evolves, complexity grows and new methodologies develop. Some issues are getting active attention – e.g. coordinating AMS extensions in SystemC, SystemVerilog and VHDL, and emerging needs for standards in designing 3D-IC. But these do not warrant a public debate among competing solutions or proposals. In fact, the industry prefers an open and inclusive dialog on not just creating the standard, but also building the entire infrastructure that provides a path to a complete solution. The first commandment of The Effective Standards continues to ring true:
Collaborate on Standards, Compete on Tools.

Peace has prevailed in the Standards World. Let peace rule the EDA standards world for a long time!

More Information:

About the Author
Yatin Trivedi is the director of Standards and Interoperability Programs at Synopsys. He represents Synopsys on the Standards Board and the Standards Education Committee (SEC) of the IEEE Standards Association (IEEE-SA), the Education Activities Board (EAB) of IEEE, the Board of Directors of IEEE Industry Standards and Technology Organization (IEEE-ISTO), and the Board of Directors of Accellera. He is Editor-in-Chief of the Standards Education Committee eZine, vice chair of Design Automation Standards Committee (DASC), member of IEEE-SA's NesCom, AudCom and ICCOM governance committees, and member of the Corporate Advisory Group (CAG). He manages interoperability initiatives as part of the corporate marketing strategic alliances group and works closely with the Synopsys University program.

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