Insight Home | Previous Article | Next Article
Issue 3, 2011
Estimating Circuit Lifetime
How long will your latest chip design last, once it's in the field? Advanced process nodes, which scale the gate oxide to a thickness of only a few molecules, are more susceptible to degradation than their predecessors. Hany Elhak, a product marketing manager at Synopsys, explains how design teams can now cost-effectively estimate the lifetime of their circuits.
The effects that cause MOS transistors to degrade with age are more prominent in advanced process nodes and the use of high-k metal-gate transistors. It's not surprising that the degradation of MOS device characteristics has become a critical measure of reliability for 45-nanometer (nm) and below processes. The issue becomes even more important for automotive electronics and other safety-critical applications.
Design teams must either factor in long and expensive testing to assess how circuit performance degrades over time, which increases manufacturing costs, or use conservative rules to overdesign the critical circuits, which increases design costs. The use of reliability analysis within simulation tools offers a more cost-effective alternative to these traditional approaches.
Why Chips Age
MOS devices age mainly because the gate dielectric and the interface between the gate dielectric and silicon degrade over time.
The hot carrier injection (HCI) phenomenon is one of the major physical mechanisms responsible for device aging. In the presence of high electric fields, carriers are injected from the drain end of the channel into the gate dielectric, changing its electrical properties over time.
Other important aging phenomena are negative bias temperature instability (NBTI) for p-channel MOSFETs and positive bias-temperature instability (PBTI) for n-channel MOSFETs, which is notably present in high-k metal-gate stacks. In both BTI cases, the amount of charge in the gate dielectric changes with the gate bias because of charge trapping and de-trapping. In the case of a constant bias, the trapped charge will continue to increase, further increasing the threshold voltage (VTH) and decreasing channel carrier mobility. This effect is strongly proportional to the device operating (biasing) temperature. In a situation where the gate voltage varies with time, some of the trapped charges can even be de-trapped, which leads to a partial recovery of the degradation that has taken place.
MOS Reliability Analysis
MOS Reliability Analysis (MOSRA) is a feature in Synopsys' HSPICE® and CustomSim circuit simulators which enables designers to simulate HCI and BTI device aging effects. It offers a robust and economical alternative to empirical overdesign or extensive lifetime testing.
MOSRA enables designers to detect reliability failures early in the design process, significantly reducing the time and cost of lifetime testing. Because MOSRA is tightly integrated with HSPICE and CustomSim, design teams can perform aging analysis as fast as the typical transient simulation runs.
- Design teams have used MOSRA in HSPICE and CustomSim to identify and debug reliability issues in design at 45nm and below by:
- Providing accurate and scalable models for both HCI and BTI, in particular, modeling the partial recovery effect that is essential for BTI
- Integrating with HSPICE and CustomSim simulation engines to perform electrical stress computation under specified operating conditions and to carry out the stress and degradation over designated time periods
- Allowing foundries and design houses to easily integrate their own custom models
- Accounting for stress accumulation - as a MOS device ages, the drain current decreases, which slows down device degradation
There are two parts to the MOSRA flow: a pre-stress simulation phase and a post-stress simulation phase. MOSRA provides a built-in aging model, as well as allowing designers to specify their own aging models to accurately predict the effect of HCI and BTI on circuit performance.
During the pre-stress ("fresh") simulation phase, the simulator computes the electrical stress of user-selected MOSFETs in the circuit, based on the MOSRA models. The calculation depends on the electrical simulation conditions of each device. The stress value from the MOSRA equation is integrated over a user-specified simulation time interval during the transient analysis. The MOSRA flow then extrapolates the result to calculate the total stress after a user-specified operation time (age).
During the post-stress phase, the MOSRA flow launches a second simulation to translate the degradation of device characteristics to performance degradation at the circuit level. The design team can run the post-stress MOSRA simulation phase on DC, AC or transient analysis.
At each MOSRA circuit operation time step, the flow considers the accumulated degradation information from previous time steps. As a result, the MOSRA takes the accumulated stress effect into account implicitly, with no need for empirical adjustments.
Figure 1: The MOSRA design flow
In Figure 1, 'EOL' refers to a MOS device's end of life, defined as the device operation time at which parameters such as saturation current degrade by a given percentage (typically, 10%) of their fresh (un-aged) values.
MOS Reliability Analysis, available in HSPICE and CustomSim, offers an accurate and efficient way for designers to analyze how IC performance will degrade with aging MOS devices.
MOSRA accurately models the HCI and BTI aging mechanisms and analyzes their impact on circuit performance using actual circuit operation and stimulus. The flow comes with a built-in aging model that is silicon-proven down to 28nm. It also gives modeling teams the flexibility to integrate their in-house models. MOSRA is integrated with the powerful engines in HSPICE and CustomSim, which enables post-stress analysis to execute as fast as pre-stress runs.
- More Information
About the Author
Hany Elhak is a product marketing manager at Synopsys with over 15 years of EDA and semiconductor experience spanning both technical and marketing responsibilities. Prior to EDA, Hany worked as an RF designer, designing RF integrated circuits for cellular and wireless networking standards. He wrote six IEEE papers on RFIC design. Hany has a BSEE and an MSEE from Ain Shams University, Cairo and an MBA with honors from UC Berkeley, Haas School of Business.