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Issue 1, 2012
Industry Initiatives: Discovery Verification IP
George Zafiropoulos, vice president, Synopsys Solutions marketing, talked to Synopsys Insight about the company’s most recent verification initiative: DiscoveryTM VIP.
Q: What is Discovery VIP?
Discovery VIP is a new generation of Verification IP (VIP). It is based on a new architecture called VIPER that we have engineered from the ground up for enhanced VIP performance, ease-of-use, configurability, portability, debug, coverage management, and extensibility.
Q: Why do we need a new generation of VIP?
The business imperative is that we need to control SoC verification cost. When it comes to creating a new system-on-chip (SoC) device, a project team will spend twice as much designing it as they do manufacturing it. Verification and embedded software are the two major drivers of the growth in the total cost-of-design, and verification now accounts for approximately half of the total hardware development cost.
This cost growth is unsustainable. It has become so expensive to verify a chip that we need to change our approach.
Q: How does Discovery VIP help control cost?
Today’s verification teams are typically three times the size of design implementation teams. We can reduce the cost of verification by helping verification engineers be more productive. Discovery VIP achieves that by reducing the time to first test, making debug easier, enabling faster simulation and allowing engineers to reach their target coverage faster than ever before.
It boosts simulation performance by up to 4x compared to previous generations of VIP.
Q: What are the trends behind the development of Discovery VIP?
Convergence is the key market trend for today’s sub-32nm, 100m+ gate devices. Convergence products, such as smartphones, tablets, and other advanced consumer products, combine several key technologies within the same device. They typically incorporate multicore CPUs, graphics, DSPs, and often support more than 10 interface protocols. They require long battery life, advanced software features, and they must be developed quickly in order to meet narrow market opportunities. Design complexity is increasing because of the need to achieve low power; in fact, some designs now incorporate more than 20 voltage domains.
And then there’s the increasing complexity of communications protocols. For example, the new USB 3.0 protocol offers 10x the performance and capability of its predecessors. But those capabilities come at a cost for verification teams: even more time spent verifying the interaction of complex protocols.
In verification terms, the consequences of verifying convergence devices are staggering: tens of millions of lines of RTL and testbench code with hundreds of thousands of assertions and terabytes of coverage data to analyze.
Q: Where does today’s VIP fall short?
Most of today’s commercial VIP is based on a mish-mash of languages and methodologies. There is typically a base model developed using C, 'e' or OpenVera, and then translation wrappers that enable the VIP to be used in the testbench’s language and methodology. The code has become bloated with all of the wrappers, creating tremendous limitations in performance and methodology.
A comprehensive wrapper will often do a reasonable job of mapping the interfaces needed to support the methodology, but still has an impenetrable black box below the level of the wrapper. More importantly, the amount of code and translation affects performance. The alternative is to reduce the wrappers and get better performance, but that comes at the expense of very limited methodology support.
Q: How did Synopsys determine what verification engineers really want?
We spoke with a lot of verification teams and completed extensive market research to identify verification engineers’ needs. In one survey, we asked both IP providers and SoC integrators to prioritize their needs. The top priority was to have broad availability for high-quality IP, which supports the verification methodologies that they use.
Unsurprisingly, SoC integrators rated performance as their next priority. RTL no longer dominates overall simulation time and the testbench, alongside the VIP, has an increasing impact on simulation and memory performance. IP developers ranked ease-of-use as their second priority, and then debug. Both of these requirements arise as a consequence of an overall increase in protocol complexity.
Because we understand users’ needs, our R&D teams have focused on delivering a new VIP architecture that delivers the features that IP providers and integrators really value.
Q: How does Discovery VIP meet verification engineers’ needs?
One of the key benefits is that Discovery protocol VIP is 100% SystemVerilog. This approach satisfies several of the important user requirements, including compliance with verification teams’ methodologies: better performance, simulator portability and ease-of-integration.
At compile time, users can choose between native support for UVM, VMM or OVM and any of the leading simulators. The VIPER VIP architecture allows verification teams to use just the methodology they are using, and to instantiate, customize, configure and control the VIP directly without affecting performance.
Writing VIP entirely in SystemVerilog means that we no longer need to provide wrappers to interface to implementation methodologies in different languages. In other words, there is no cross-language overhead because verification teams can now implement their VIP natively in the target methodology without translation or remapping. Therefore, the VIP code is optimized for performance.
Based on 25 years of innovation, the new generation of Synopsys VIP is designed to help engineers achieve accurate, low-cost design to meet their SoC design requirements.
- More Information:
George Zafiropoulos, Vice President of Solutions Marketing at Synopsys
George Zafiropoulos brings more than 25 years of EDA marketing and technical management expertise to his role as vice president, solutions and verification marketing, at Synopsys. In this role, he is responsible for Synopsys' key vertical markets, low power and system-to-silicon verification.
Prior to joining Synopsys, George worked as vice president of verification marketing at Cadence Design Systems. Before that, he was vice president of marketing for Quickturn Design Systems, which was acquired by Cadence in 1998. Zafiropoulos also held a senior management position with Daisy Systems, an EDA hardware and software provider.
George holds a bachelor’s degree in management from Pepperdine University, Malibu, California.