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Issue 3, 2011
In-Design Physical Verification: Automatic DRC Repair
Design teams need to run more design rule checks (DRC) than ever before in order to comply with the latest manufacturing processes. Synopsys' Paul Friedberg and Stylianos Diamantidis explain how design teams can use automatic DRC repair, a feature of in-design physical verification, to automatically detect, repair and revalidate signoff DRC violations.
Traditionally, the interface between design and manufacturing has followed an "implement-then-verify" flow. Although the design is "clean" within the implementation environment after place and route, to achieve signoff for manufacturing, the design team must next use an independent tool to physically verify the design again. Signoff DRC can flag corner-case issues that the router technology may not, which the design team has to then repair and revalidate (Figure 1).
Figure 1: Traditional "implement-then-verify" approach to physical design
Once the design team has identified the signoff-level violations, they must pass the error database back into the implementation environment, manually correct the violating geometries and, if necessary, modify the router technology file to achieve a cleaner route of the entire design.
The design team then has to repeat the full implementation cycle to achieve timing closure, as well as repeat physical signoff using the independent verification tool. This cycle repeats until there are no remaining DRC violations – a process that can adversely impact meeting tapeout deadlines.
Design teams can drastically reduce the number of iterations required to achieve zero DRC violations by taking an "in-design" approach to physical verification. This approach allows physical implementation and verification tools to collaborate by performing signoff-level DRC analysis during implementation. Identifying DRC violations at this early stage enables the design team to fix them more effectively and at minimal cost.
Automatic DRC Repair Flow
Although in-design verification reduces the time it takes for design teams to identify potential DRC issues, they still face the problem of fixing the violations, which takes time and expertise.
By adding automated repair capabilities (Figure 2), in-design physical verification becomes even more productive. Automated repair enables the tools to correct the majority of signoff DRC violations that are identified, leaving minimal violations to correct manually.
Figure 2: "In-design" flow with automated repair
Intelligent integration between Synopsys' IC Compiler and IC Validator products provides the foundation for automatic DRC repair (ADR). It enables designers to review DRC results in a familiar environment, at which point they can decide which rules they want to target with ADR.
ADR uses heuristic-driven repair to achieve a balance between high success rates and nominal layout disruption. Heuristic-driven repair has several benefits over deterministic approaches – it's more scalable, faster to converge and the results are less disruptive to the chip's timing.
Design teams need no in-depth knowledge of the targeted design rules in order to set up the ADR flow, and they can specify the level of persistence for repair/validation attempts to actively tune the repair rate against the flow runtime. Operations on targeted geometries are extremely fast: ADR completes roughly three repairs per second.
Overall, the ADR flow offers design teams much better performance and productivity than the alternative of manual fixing and validation.
For a 45-nanometer (nm) design containing about 800 thousand instances, ADR targeted 550 total signoff-level DRC violations and repaired 432 (79%) within two iterations of automated repair.
ADR performed extremely well for spacing and width violations on M1-M3 and several via layers. In particular, ADR repaired 392 M1 line-end spacing violations arising between polygons in lower-level library cells and routing-level signal route.
Despite the high repair rate, ADR resulted in highly localized changes to the design and therefore had negligible timing impact. The slack is virtually unchanged (+/-1 ps) for 99% of the 15,000 most critical paths in the design.
ADR didn't address violations that were associated with designated immovable objects, such as pins or power straps, or violations that would have required a more intrusive repair than specified. This is to be expected, as ADR's first priority is minimal disruption to the existing layout.
The design team benefited from an 80% fix rate with negligible timing impact, achieving successful repairs on multiple metal and via layers. What would have taken 1-2 days of tedious work was completed, without user input, in less than 2 hours on a standard 4-CPU hardware configuration.
As the complexity and number of design rules continues to increase for advanced semiconductor processes, the traditional approaches to physical verification after design closure are becoming unsustainable. Design teams can no longer afford to spend days or weeks making manual fixes to achieve signoff-level verification.
- In-design physical verification with IC Compiler and IC Validator now features automatic DRC repair. The flow enables automatic repair of signoff-level DRC violations. ADR allows designers to quickly fix the majority of signoff DRC violations, which minimizes the need for late-stage manual fixes and eliminates entire design iterations. The ADR flow delivers:
- Signoff-quality independent DRC analysis
- High rate of router-driven repair with minimal physical/timing impact
- Automatic, incremental validation of repaired layout regions
- Flexibility to specify particular rules and the number of repair loops to run
- Push-button ease of use
- More Information
About the Authors
Paul Friedberg develops and manages the deployment of physical verification applications at Synopsys. His area of special focus is In-Design physical verification with IC Validator and IC Compiler. He holds a Ph.D. in Electrical Engineering from the University of California, Berkeley.
Stylianos Diamantidis drives development and commercialization of physical verification technologies at Synopsys. He is currently leading In-Design physical verification with IC Validator and IC Compiler. Stylianos has more than 15 years of experience in engineering, management and marketing of software products for the semiconductor industry. In addition to physical verification and DFM, he has an established track record in design verification, logic simulation, test and IP. He holds an M.S. in Electrical Engineering from Stanford University, California.