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Issue 3, 2013

Technology Update
Scalable Architectures for Analog IP on Advanced Process Nodes

Carlos Azeredo-Leme, Senior Staff Engineer for DesignWare Analog IP, Pedro Figueiredo, Staff Engineer for DesignWare Data Converter IP, and Manuel Mota, Technical Marketing Manager for Analog IP, Synopsys, explain why the successive approximation register analog-to-digital converter (ADC) is the architecture of choice for medium- and high-speed ADCs targeting 28-nm processes and beyond.

Design teams tackling mixed-signal System-on-Chip (SoC) designs face a perennial problem: how to get the best out of the latest advanced process technologies when it comes to implementing their analog IP.

While digital logic scales to take advantage of the speed and area benefits of new process geometries, analog structures won’t readily scale. Nevertheless, design teams are still expected to deliver new products that offer more functions and higher performance while consuming less power at a lower cost. Analog IP is too often the ‘thorn in the side’ of the low-power digital SoC.

In order to scale their analog IP, design teams need to take a different approach to mixed-signal design and utilize analog architectures that better suit the latest digital process technologies.

Applications that typically depend on mixed-signal SoCs include mobile communications, wireless applications and multimedia devices, such as set-top boxes and digital TVs. The common factor in these products is the need to take analog signals from radio transmitters, wireline transceivers and sensors. One of the key tasks for mixed-signal SoCs is to convert the incoming analog signal into a digital signal for processing on the chip using an accurate analog-to-digital converter, or ADC.

ADC Architectures for Advanced Process Nodes
Today, design teams can choose from a number of different ADC architectures. Each architecture has different characteristics – some are better at supporting higher resolution accuracy, others offer better support for high sample rates (Figure 1, Table 1).

Scalable Architectures for Analog IP on Advanced Process Nodes
Figure 1: How today’s ADC architectures compare for sample rate and resolution

Scalable Architectures for Analog IP on Advanced Process Nodes
Table 1: Comparison of the attributes of ADC architectures

The successive approximation register (SAR) algorithm digitizes the input signal step by step until it finalizes the conversion. Traditional implementations of the algorithm reuse the same hardware for each step, which means that it requires a clock rate that is at least ‘N+1’ times the sample rate, where N is the number of bits of resolution. For example, a 10-bit ADC will require a clock rate that is 11x the sample rate. This implementation constraint limits the usefulness of the SAR algorithm to moderate-speed and medium-to-high resolution applications.

Figure 2 shows the basic block diagram of a SAR ADC including a sample-and-hold (S&H), a comparator, a digital-to-analog converter (DAC) and a logic block (SAR). The input signal (Vin) is stored on the sample-and-hold and is successively compared to the output of the DAC, whose input codes are set by a logic block, depending on the result of the previous comparisons.

Scalable Architectures for Analog IP on Advanced Process Nodes
Figure 2: Basic block diagram of a SAR ADC

In contrast to other ADC architectures, the SAR ADC implementation does not rely on having multiple stages with large, power-hungry gain amplifiers. The analog element of the design is a single-stage comparator, which is inherently compact and low power. It is possible to make further design optimizations, for example the sample-and-hold can be merged with the DAC by the use of switched capacitors, further reducing the area and eliminating interfaces. Another benefit is that unlike many analog structures, the SAR ADC is not overly sensitive to the analog characteristics of the silicon process for its correct operation.

The simplicity and efficiency of the SAR ADC makes it an attractive option for mixed-signal design teams because many of its attributes are silicon-friendly for advanced geometry process nodes.

Evolving the SAR Architecture for High Speed and Low Power
While the traditional SAR circuit has many favorable attributes for SoC integration, including its simplicity and compact size, its main drawback is that it is too slow for very high-performance systems. As explained above, it needs a clock speed that is a high multiple of the sample rate. Furthermore, to support higher resolutions, the traditional design needs large capacitor arrays, which add to the circuit’s size and power demands.

Reducing SAR Clock Speed
By creating an internal clock to control the SAR and DAC blocks, which is asserted every time the comparator completes a decision, it is possible to remove the need for a high-speed clock. This approach enables design teams to use a clock rate that is equal to the sampling rate.

Reducing Capacitance
The capacitor array doubles for every additional bit of resolution. For example, a 12-bit ADC will need an array that’s 4096x the minimum capacitance. Big capacitors take a lot of area and power. It is possible to reduce the capacitance by breaking the array in two by using a floating secondary array to process the lower order bits.

Optimizing the Capacitor Array
Several other circuit techniques can be applied to the capacitor array in order to reduce noise and power. For example:
  • Area-efficient digital calibration techniques can be used to measure and correct capacitor-matching errors.

  • Alternative switching schemes can reduce the inefficient charging of capacitor plates between Vref and ground, which saves charging energy and reduces power.

  • By including redundancy in the conversion algorithm, it is possible to correct for initial errors and allow the bit decisions to run faster by reducing the voltage settling time required in the comparator input.

  • It is possible to speed up the SAR algorithm even more by parallelizing the architecture using multiple time-interleaved SAR ADCs. For example, a 4x speedup will require four interleaved ADCs.

Synopsys SAR ADC IP for 28-nm Processes
Synopsys has developed a new generation of ADCs for 28-nm processes based on the high-speed, low-power SAR architecture and building on many of the optimization techniques outlined above. By engineering the architecture to take advantage of the high-speed digital qualities of the latest semiconductor processes, Synopsys has produced analog IP that better serves the needs of design teams tackling advanced mixed-signal SoCs. The characteristics of the circuit are such that the performance and power benefits will scale with even smaller process nodes than 28-nm – a major benefit for mixed-signal SoC design teams.

Using the new SAR architecture, a 12-bit ADC converting at 80 MSPS (million samples per second) will dissipate a third of the power compared to a similar ADC built using the traditional pipeline architecture, and consume one-sixth of the area. The Synopsys SAR-based 12-bit ADCs support sample conversion rates of up to 320 MSPS.

The Synopsys ADC is suitable for use in applications that require a low duty-cycle or where the time to availability of the sample is critical. This is because the ADC stores and reuses its calibration constants, which reduces the power-up time; the short latency of the architecture and the relatively modest clock speed compared to the sample frequency also help reduce the time to convert.

Ease of Integration
Synopsys has kept with the same top-level interface as the previous generation of pipeline ADCs, which will make it easier for design teams to integrate the part when refreshing legacy designs to target new 28-nm process nodes.

Synopsys’ DesignWare® Analog IP portfolio includes:
  • SAR-based High-Speed Data Converter IP in 28-nm processes
  • 12-bit 320 MSPS, 160 MSPS and 80 MSPS Receive ADCs
  • 12-bit 600 MSPS Transmit DACs
  • 3 GHz Low Jitter Clock Generating PLLs
  • 12-bit General Purpose 5 MSPS ADCs
  • 20 MSPS DACs
  • 10-bit 300 MSPS Video DACs
  • 96-dB Analog Audio Codecs

By using digitally-enabled analog techniques and developing new architectures, Synopsys has created an analog and mixed-signal IP portfolio that now enables design teams to take advantage of SoC silicon scaling to achieve better power and area from their analog IP as well as their digital logic.

This approach is highly beneficial for design teams working on advanced devices that depend on having high-performance, low-power analog interfaces. This includes mobile communications applications including smartphones and tablets, wireless connectivity, digital TV and satellites, and many other multimedia interfaces.


More Information

About the Author
Carlos Azeredo-Leme is a senior staff engineer for DesignWare Analog IP. Prior to joining Synopsys, he was co-founder and a director of Chipidea Microelectronics, where he held the position of chief technical officer. There, he was responsible for complete mixed-signal solutions, analog front-ends and RF for audio, power management, cellular and wireless communications, and RF transceivers. He is a teacher at the Technical University of Lisbon (UTL-IST) in Portugal. His research interests are in analog and mixed-signal design, focusing on low power and low voltage. Carlos holds an MSEE from Technical University of Lisbon (UTL-IST) in Portugal and a Ph.D. from ETH-Zurich in Switzerland.

Pedro Figueiredo is a staff engineer for the DesignWare Data Converter IP product line at Synopsys. He has been working on the development of advanced signal conversion solutions since 1999 when he joined Chipidea Microelectrónica, which was later acquired by MIPS and then by Synopsys in 2009. From 1997 to 1999, Pedro worked in the Analog and Mixed-Mode Circuits Group at the Institute for Systems and Computer Engineering (INESC) in Portugal. He has published a variety of technical papers in leading international journals and conferences and also authored the book, “Offset Reduction Techniques in High-Speed Analog-to-Digital Converters”, published by Springer in 2009. Pedro holds a Ph.D. in Electrical and Computer Engineering from Technical University of Lisbon (UTL-IST) in Portugal.

Manuel Mota is a technical marketing manager for analog IP at Synopsys and is responsible for the DesignWare Data Converter and Audio Analog IP product lines. He brings more than 13 years of technical and marketing experience in analog IP to his position. Prior to Synopsys, Manuel held product marketing, business development, and IP design positions at MIPS Technologies and Chipidea Microelectronica. Manuel holds a Ph.D. in Electronic Engineering from Technical University of Lisbon (UTL-IST) in Portugal which he completed while working at CERN (Switzerland) as a Research Fellow. He has authored multiple technical papers and presented in several technical conferences on analog and mixed signal design.


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