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Issue 2, 2011
DesignWare® IP: Product Updates and Customer Successes
Synopsys enables designers to reduce integration risk and accelerate time-to-market by providing high-quality, silicon-proven interface IP, analog IP, embedded memories, logic libraries, processor cores and SoC infrastructure IP. As the leading provider of semiconductor IP solutions for systems-on-chips (SoC) designs, Synopsys is continuously enhancing its DesignWare IP portfolio. The following highlights some recent product updates and customer successes.
Figure 1: Synopsys DesignWare IP Portfolio
SATA IP Receives SATA-IO 6 Gb/s Certification
The DesignWare SATA host and device digital controllers and PHY IP have successfully passed the Serial ATA International Organization (SATA-IO) 6Gb/s certification. To achieve certification, the DesignWare SATA IP solutions maintained a 6 Gb/s data transfer rate and passed more than 200 tests that span electrical, digital and system interoperability as defined in the SATA Revision 3.0 specification.
In addition, the DesignWare SATA digital controllers support the new features documented in the SATA Revision 3.0 specification, including streaming Native Command Queuing (NCQ) and power management states. By providing silicon-proven and certified SATA IP that support the latest features, Synopsys enables designers to lower integration risk and speed adoption of SATA 6Gb/s data transfer rates. Learn more.
ARC™ Sound IP First to Support Dynamic Resolution Adaptation Audio Standard
The DesignWare ARC Sound DRA decoder supports the Chinese National HD audio standard that is included in the Blu-ray™ Disc specification and is the first optimized implementation available as part of a comprehensive, commercial audio IP solution. The highly efficient AS211SFX and AS221BD audio processors require 18 MHz to run the optimized DRA decoder for Chinese Digital Broadcast (2.1 channel) and only 134 MHz for Blu-ray Disc (7.1 channel).
The DesignWare ARC Sound DRA codec together with the DesignWare ARC Sound audio processors enable original equipment manufacturers (OEMs) and SoC designers to deliver an enhanced, high-quality, high-definition audio experience in a wide variety of applications used in Chinese digital broadcasting, digital home theater systems, internet streaming and personal media players. Learn more.
SuperSpeed USB 3.0 xHCI Host Controller Receives USB-IF Certification
The xHCI specification provides a standardized method for SuperSpeed USB (USB 3.0) host controllers to communicate with the USB 3.0 software stack. To achieve certification, the IP must support the new U1 and U2 power modes as well as all four USB transfer speeds, including SuperSpeed (5.0 Gbps), Hi-Speed (480 Mbps), Full-Speed (12 Mbps) and Low-Speed USB (1.5 Mbps). Synopsys is the only USB IP provider with both certified SuperSpeed USB 3.0 Host and Device IP.
The complete DesignWare SuperSpeed USB 3.0 IP solution offers a unified architecture, enabling designers to significantly lower integration risk by eliminating the requirement to manage two distinct USB 2.0 and USB 3.0 datapaths in their system-on-chip (SoC) designs. Optimized for small area and low-power, the DesignWare SuperSpeed USB 3.0 Host Controller is already in products that are in mass production. It is ideal for battery-powered, portable devices. Learn more.
Interface PHY and Embedded Memory IP for TSMC 28-nm Processes
Synopsys’ close collaboration with TSMC has resulted in a broad portfolio of IP for the TSMC 28-nm process including interface PHYs for SuperSpeed USB 3.0, USB 2.0, HDMI, PCI Express®, DDR and SATA as well as embedded memories. Availability of DesignWare IP at this leading TSMC node enables designers to incorporate more functionality into their most advanced SoCs while meeting low power and small silicon area requirements.
The collaboration also enabled Synopsys to achieve USB logo certification for the DesignWare USB 2.0 picoPHY IP in TSMC’s 28-nm process. The USB 2.0 picoPHY IP demonstrates a robust design architecture that can withstand rigorous process, voltage and temperature variations. In addition, DesignWare Embedded Memories have also achieved positive silicon results for TSMC's 28-nm process.
Over the years, the longstanding relationship between the two companies has enabled Synopsys to develop its DesignWare PHY IP from 180-nm to 28-nm process technologies, allowing design teams to integrate key industry standard interfaces into their designs with less risk and improved time-to-market. Learn more.
Next-Generation Data Converters
The next-generation of DesignWare Data Converters delivers an improvement of over 50% in power with smaller area compared to the previous generation of data converters. Optimized for mobile broadband wireless communication applications such as WiFi, WiMAX, LTE, and digital TV reception, the data converters can achieve high sampling rates with outstanding dynamic performance, while processing signal bandwidth beyond 100 MHz.
- The data converters consist of high-performance ADCs and DACs for broadband wireless and wireline communication SoCs including:
- 10-bit and 12-bit pipeline ADCs running up to 250 MSPS in single channel and dual channel configurations
- 14-bit current steering DACs running up to 400 MSPS in single channel and dual channel configurations
Support for Final Release of PCI Express 3.0 Specification
Synopsys is the first IP provider to support the final version of PCI Express 3.0 specification recently released by the PCI Special Interest Group (PCI-SIG®). In addition, Synopsys has enhanced its DesignWare digital controllers with new features including support for the latest PIPE 3.0 specification (v0.9), PCI-SIG engineering change notifications (ECNs), 256-bit datapath and embedded DMA engine. All of these enhancements provide performance improvement for the PCI Express interface.
Synopsys’ portfolio of silicon-proven digital controllers – comprising of endpoint, root complex, switch and dual mode cores – enables designers to integrate the 8.0 GT/s PCI Express 3.0 interface into their SoC designs with less risk and improved time-to-market. Learn more.
Data Converters for SMIC 65LL
The availability of silicon-proven DesignWare Data Converters in SMIC's popular 65-nanometer (nm) low leakage (LL) process technology enables designers at this popular technology node to improve their chips' power efficiency, ease integration efforts and reduce silicon costs.
- Targeted at battery-powered broadband wireless communications (WiFi802.11n, LTE, WiMAX) and digital TV reception (CMMB, DVB) applications, the comprehensive portfolio of low power, compact data converters including high-speed analog-to-digital converters (ADCs) and digital-to-analog converters (DACs) including:
- 10-bit 80 MSPS dual pipeline ADC
- 10/8-bit 2 MSPS SAR ADC with differential 8:1 input mux
- 12-bit 160 MSPS current steering IQDAC
- 11-bit 20 MSPS general purpose DAC
Next-Generation Universal DDR Controller
The enhanced Universal DDR Memory Controller delivers up to 30% lower latency and 15% higher throughput than the previous generation controller and offers new features like high-priority bypass and configurable ‘look-ahead.’
The high-priority bypass option enables designers to improve latency by bypassing the scheduling algorithm, allowing immediate access to the DRAM. Configurable 'look-ahead' provides intelligent scheduling to maximize throughput by prioritizing out-of-order transactions to the DRAM, so designers can make trade-offs between area and performance.
The memory controller offers a DFI 2.1-compliant interface to the DDR PHY, delivers memory system performance up to 2133 Mbps and supports the DDR3, DDR2, LPDDR and LPDDR2 SDRAM standards. Learn more.
Fairchild Achieves First-Pass Silicon Success with DesignWare USB 2.0 nanoPHY
Using Synopsys' DesignWare USB 2.0 nanoPHY IP, Fairchild Semiconductor achieved first-pass silicon success for its FUSB2500 UTMI+ Low-Pin Interface (ULPI) USB On-The-Go (OTG) transceiver chip that targets the high-end handset market.
Fairchild selected the DesignWare USB 2.0 nanoPHY because it was low in power and area, and offered technical features such as auto-detect functionality and ULPI interface. The tunability of the PHY enabled Fairchild to conduct post-silicon adjustments without incurring the cost of a metal respin. The convenient access to a knowledgeable, responsive technical support team enabled Fairchild to easily integrate the IP within weeks, focus on its product differentiation and meet its critical 14-month project schedule.
Speaking of Synopsys’ DesignWare IP, Jerry Johnston, senior director of switch and interface at Fairchild, said, “With a tight development schedule and complex design requirements, we wanted to partner with a trusted and established IP vendor such as Synopsys. The Synopsys DesignWare USB 2.0 nanoPHY IP offered us a solution that would incorporate all of our design needs and meet our time-to-market window. Synopsys' DesignWare IP is a high-quality product and will continue to be a key element of our future product developments." Learn more.
Wilocity Tapes-Out Multi-Gigabit SoC with DesignWare IP
Using DesignWare PCI Express, Embedded Memories and Logic Libraries from Synopsys and with assistance from Synopsys Professional Services, Wilocity has successfully taped-out its multi-gigabit Wireless Gigabit Alliance-compliant SoC. Wilocity’s chip is based on the Wireless Gigabit Alliance (WiGIg) and IEEE802.11ad draft specification and is used for a wide range of applications, including IO, networking and video.
Leveraging Synopsys tools, DesignWare IP and Professional Services, Wilocity was able to reduce power consumption in some of the more complex arithmetic clusters by approximately 50%, increase performance by 65% and improved utilization by up to 70% compared to their previous design.
Speaking of the collaboration, Ido Naishtein, director of physical design at Wilocity, said, “As consumers demand greater mobility, device manufacturers are requiring advanced mobile computing platforms that enable them to deliver thin and light devices without sacrificing performance and functionality. Wilocity's use of proven DesignWare IP and close collaboration with Synopsys Professional Services has enabled us to successfully produce multi-gigabit wireless chips that are optimized for today's mobile devices." Learn more.