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Issue 1, 2012
The Fast Track to 3D-IC Testing
Three-dimensional integrated circuit (3D-IC) systems offer the potential to deliver significant improvements in performance, power, functional density, and form factor over other packaging integration techniques. Despite substantial progress toward realizing 3D-IC systems, a variety of design, manufacturing, packaging, and testing issues still need to be addressed before cost-effective, high-volume production can be achieved. In this article, Chen-An Chen, deputy engineer, Industrial Technology Research Institute (ITRI), Yee-Wen Chen, technical deputy manager, ITRI, Chris Allsup, marketing manager, Synopsys and Adam Cron, principal engineer, Synopsys discuss the test challenges and solutions, highlighting a design-for-3D-test architecture and implementation flow developed by researchers at ITRI based on the Synopsys test solution.
2.5D Before 3D
Advances in manufacturing and packaging technologies have already brought “2.5D” platforms within reach of early adopter design teams: 2.5D IC integration offers the potential to deliver a tighter form factor than standard systems-in-package by mounting multiple dies atop a common electrical interface, called a silicon interposer, and connecting them together with wires that run through the interposer . The system I/Os are connected to the underlying package substrate using vertical Through Silicon Vias (TSVs), essentially cylindrical metal posts that extend partway through the interposer (Figure 1).
Figure 1: 2.5D configuration with silicon interposer
But when it comes to delivering on the integration benefits mentioned above, 3D die stacking  holds the greatest promise. With this approach, TSVs are etched deep into the substrate and the wafers thinned down to less than 50 microns. Many dies can then be stacked vertically on top of each other and connected together by TSVs (Figure 2). A combination of the two techniques resulting in a heterogeneous system of multiple die stacks would utilize a silicon interposer to connect all the bottom dies in the same way as 2.5D-IC packages.
Figure 2: 3D configuration with face-to-back bonding of two stacked dies connected by TSVs
The design of the first 3D-IC systems is now underway, thanks to the development of standards by organizations such as IEEE, JEDEC, SEMI, and Si2 in cooperation with semiconductor and electronic design automation (EDA) companies. For example, in October 2011, Samsung and Micron Technology announced the creation of a consortium to accelerate industry collaboration for the development of an open interface specification for Samsung’s Hybrid Memory Cube, which delivers “unprecedented system performance and bandwidth” in part by employing vertically stacked memories connected through TSVs. In spite of early progress, a range of technical obstacles still need to be overcome to achieve cost-effective, mass production of 3D-IC systems. We will now turn to the challenges confronted when testing them in a high-volume setting.
Testing in 3D
One basic approach to 3D-IC testing involves performing a post-bond test after each die has been bonded to the stack. The goal is to test portions of the system that could have been damaged during the bonding process. Because it is not viable to “un-bond” a die subsequently found to be defective, one study  maintains that performing a separate pre-bond (i.e., standalone) test to identify a Known Good Die (KGD) for stacking is more cost-effective than relying solely on post-bond testing to identify a defective die that has already rendered the entire system defective.
However, the economics of pre-bond testing have yet to be fully characterized, and one of the key challenges is how to apply the KGD test. With the exception of the bottom die, no probe pads exist for pre-bond testing because all the I/Os are accessible only through TSVs topped by fine-pitch micro-bumps, which are arrayed on both sides of the die. Standard probe equipment applies tests only on a single side and even state-of-the-art production systems do not meet the fine-pitch and I/O bandwidth requirements of 3D-ICs. Moreover, it is difficult to perform pre-bond tests without damaging the micro-bumps or deforming the thinned wafers .
Efforts are underway to deliver probe systems that facilitate probing on fine-pitch micro-bumps. Rocking Beam Interposer (RBI) technology  in membrane probe cards improves probing accuracy and minimizes bond pad damage. Contactless probing  may also prove viable. At this time, however, these solutions are still a work-in-progress for meeting 3D-IC probing requirements. Likewise, the test challenges specifically related to the handling of thinned wafers and thinned dies remain formidable [4, 7], and in 2010, SEMI created a taskforce specifically to define requirements and develop standards for the reliable handling and shipping of thin wafers.
These and other test infrastructure challenges must be properly addressed before 3D-ICs can be tested cost-effectively in high volume. Yet compared with these challenges, the design-for-test (DFT) challenges for 3D-ICs are much easier to overcome, as we’ll see in the sections that follow.
Test Automation Evolves
Although there are new failure mechanisms due to defects caused by wafer thinning and by TSV filling, alignment, and bonding, their fault effects appear to be the same as those encountered in two-dimensional (2D) designs. Therefore, conventional stuck-at and transition-delay automatic test pattern generation (ATPG) can be used or extended to test 3D-ICs. For example, slack-based transition delay tests that target small delay defects and bridging tests that target bridging faults are already in use today to meet ultra-high test quality requirements. With the advent of 3D-ICs that offer smaller form factors and higher performance than current 2D designs, these advanced tests—already available in Synopsys’ TetraMAX ATPG product—become necessary for screening 3D systems.
In addition, greater system complexity of 3D-ICs demands tighter control of dynamic power consumption, which differs pre-bond versus post-bond (since TSVs are used to distribute power up the stack in the latter case). Advanced power management techniques, such as power-aware ATPG and power domain-based testing, are required to control power consumption and avoid false failures during 3D-IC testing. Power-aware ATPG generates patterns that limit both shift mode and capture mode power to functional levels based on a designer-specified power budget. Power domain-based test generates patterns in compliance with a design’s functional power states to reduce both dynamic and leakage power and avoid IR-drop issues. These advanced capabilities in the Synopsys test solution already have been successfully deployed to limit false failures on the tester, and will be essential for managing power during testing of 3D-ICs, which are also susceptible to increased thermal density and thermal variation .
Extensions to existing test automation that address very specific 3D-IC testing requirements include the ability to insert and connect TSV ports and related logic in a design, and the ability to generate “loopback” tests that allow data to be applied to and captured from the TSV I/Os to verify their functionality during KGD testing. For TSV connectivity tests, TetraMAX ATPG uses “dynamic bridging” fault models to generate at-speed patterns that can target time-sensitive shorts between TSV I/Os.
Design for 3D Test
Although DFT standards for 3D-IC testing are still evolving (IEEE Std P1838 is the proposed architecture standard for test access), it is currently possible to implement 3D DFT architectures based on existing standards and 3D test flows based on existing test automation solutions and their extensions. At ITRI, we have developed a practical DFT architecture for 3D-IC testing that combines elements of IEEE Std 1149.1 and core-wrapping for test access, a flexible user-defined instruction (UDI) set, and pin-limited scan compression. ITRI’s proposed DFT/ATPG implementation flow uses Synopsys’ synthesis-based test solution, which is comprised of DFTMAX compression and TetraMAX ATPG .
Some of the KGD test access issues discussed previously can be avoided by utilizing a small number of dedicated probe pads for pre-bond testing. Although there is an area overhead penalty for inserting “sacrificial” probe pads that will only be used for testing, ITRI believes the cost benefits of having KGD before stacking outweigh the negatives. For pre-bond test access, all dies use the IEEE Std 1149.1 serial interface for both test instructions and test data; the six test signals are the JTAG ports (TCK, TMS, TDI, TDO, and TRSTN) plus a ShiftEn, which affords some additional DFT flexibility. Our DFT architecture combines the boundary scan registers and die wrappers with the internal scan chains in the compression logic synthesized by DFTMAX (Figure 3). Utilizing the pin-limited test feature in the product to compress the ATPG patterns is key to reducing test application time and lowering the cost of 3D-IC testing.
Figure 3: ITRI’s architecture uses the pin-limited test feature in DFTMAX to lower the cost of 3D-IC testing
For post-bond test access to dies further up the stack, the test interfaces on each die are daisy-chained up the stack and back down again (Figure 4). Generic boundary scan instructions as well as user-defined instructions control the logic that selects test data going up or coming down the stack and determine the different kinds of scan tests that are performed. The architecture supports interconnect testing between neighboring dies in the stack and has the flexibility to test multiple dies in the stack simultaneously.
Figure 4: ITRI’s test access mechanism provides a flexible and convenient method to control test data
ITRI’s test implementation flow (Figure 5) requires configuring the scan chains for wrapper and boundary scan insertion using DFTMAX, then specifying how these chains will be incorporated into the compressor/decompressor (CODEC) logic. When the CODECs are synthesized, DFTMAX generates the test protocol file. TetraMAX ATPG then processes it to generate the test patterns for the various test modes, such as INTEST, EXTEST, SERIALIZE, MBIST, etc. The KGD patterns for the pre-bond tests are subsequently translated into stack-level patterns for the post-bond tests.
Figure 5: 3D-IC test pattern generation flow using Synopsys’ synthesis-based test solution
There are additional capabilities in the Synopsys test solution which provide access to embedded test and debug features via the IEEE Std 1149.1 Test Access Port (TAP) that are especially beneficial for 3D-IC testing and diagnosis. One example is the DesignWare Self-Test and Repair (STAR) Memory System, which enables embedded test and repair of memories and works in conjunction with DFTMAX. The system receives instructions via the JTAG TAP and uses IEEE Std 1500 interfaces to provide the necessary test access and isolation for memories that reside on all the dies in the stack, including Wide I/O mobile memory with TSV interconnects. Another example is self-test of high-speed SERDES I/Os, for which the DesignWare IP has built-in TAP access to characterization and debug resources.
Both of these capabilities seem to be compatible with IEEE Std P1687, the proposed instrumentation standard, and are examples of the type of instrument access mechanisms that are critical for successful 3D-IC product certification and deployment. In addition to the standards we have discussed, Synopsys’ test solution employs STIL (IEEE Std 1450.x) and CTL (IEEE Std 1450.6) as mainstream interfaces to other systems in the electronics design and manufacturing industry, and as means to enable 2.5D- and 3D-IC testing.
Although advances in manufacturing and packaging technologies have brought 2.5D systems within reach, high-volume production of 3D-IC integration is still a few years away due to a number of technical and business hurdles that have yet to be overcome, some of which concern test. Test automation is a critical part of 3D-IC requirements, and will continue to evolve to meet the future needs of the semiconductor industry as experience grows and standards for testing 3D-ICs converge. Despite the dearth of ratified standards, organizations like ITRI are already using Synopsys’ synthesis-based test solution to rapidly develop their 3D-IC test flows. Advanced capabilities proven to be effective at testing today’s most complex 2D systems-on-chip—slack-based transition delay ATPG, power-aware and power domain-based testing, pin-limited compression, and embedded self-test for debug and diagnosis—will be essential for achieving the quality and cost requirements of tomorrow’s 3D-ICs.
 Sunohara, M., Tokunaga, T., Kurihara, T., Higashi, M., “Silicon Interposer with TSVs (Through Silicon Vias) and Fine Multilayer Wiring,” Electronic Components and Technology Conference, 2008.
 Chen, K.N., Tan, C.S., “Integration Schemes and Enabling Technologies for Three-Dimensional Integrated Circuits,” IET Computers & Digital Techniques, Volume 5, Issue 3, 2011, Pages 160–168.
 Taouil, M., Hamdioui, S., Beenakker, K., Marinissen, E.J., “Test Cost Analysis for 3D Die-to-Wafer Stacking,” 19th IEEE Asian Test Symposium (ATS), 2010, Pages 435–441.
 Bottoms, W.R., “Test Challenges for 3D Integration (an invited paper for CICC 2011),” IEEE Custom Integrated Circuits Conference (CICC), 2011, Pages 1–8.
 Marinissen, E.J., Daenen, T., Dupas, L., Van Dievel, M., Hanaway, P., Kiesewetter, J., Smith, K., Strid, E., Thärigen, T., “Wafer Probing on Fine-Pitch Micro Micro-Bumps for 2.5D- and 3D-SICs,” IEEE South-West Test Workshop–San Diego, California, June 2011.  Sayil, S., “Optical Contactless Probing: An All-Silicon, Fully Optical Approach,” IEEE Design & Test of Computers, Volume 23, Issue 2, 2006, Pages 138–146.
 Zoschke, K., Wegner, M., Wilke, M., Jurgensen, N., Lopper, C., Kuna, I., Glaw, V., Roder, J., Wunsch, O., Wolf, M. J., Ehrmann, O., Reichl, H., “Evaluation of Thin Wafer Processing Using a Temporary Wafer Handling System as Key Technology for 3D System Integration,” 60th Proceedings of the Electronic Components and Technology Conference (ECTC), 2010, Pages 1385–1392.
 Chen, Y., Kursun, E., Motschman, D., Johnson, C., Xie Y., “Analysis and Mitigation of Lateral Thermal Blockage Effect of Through-Silicon-Via in 3D IC Designs,” Low Power Electronics and Design (ISLPED), 2011, Pages 397–402.
 DFTMAXTM Compression User Guide, Version F-2011.09, September, 2011; TetraMAX® ATPG User Guide, Version F-2011.09-SP1, October, 2011, Synopsys, Inc.
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About the Authors
Chris Allsup, marketing manager in Synopsys’ synthesis and test group, has more than 20 years combined experience in IC design, field applications, sales, and marketing. He earned a BSEE degree from UC San Diego and an MBA degree from Santa Clara University. Chris has authored numerous articles and papers on design and test.
Adam Cron, principal engineer at Synopsys, is part of the Test Automation Corporate Applications Engineering team and has been with the company for 14 years. A Syracuse University graduate, Adam has worked in test-related fields at Motorola and Texas Instruments for a total of 25 years in the industry. Adam has worked on many IEEE standards efforts, is currently vice-chair of IEEE Std P1838, and is an IEEE Golden Core recipient.
Chen-An Chen, deputy engineer for the design automation technology division at ITRI, has been with the company for 3 years. He earned a MSEE degree from National Changhua University of Education. His research interests include design-for-testability, low-power design and 3D-SIC testing exploration. He is currently a member of IEEE Std P1838.
Yee-Wen Chen is a technical deputy manager for the design automation technology division at ITRI. She earned a MSEE degree from National Taiwan University. She has more than 10 years experience in chip design and IC design flow.
This article was initially published in EE Times on January 16, 2012.