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Issue 4, 2011

Technology Update
Next-Generation Low-Power Data Converters for High-Performance Communication Applications

Manuel Mota, a technical marketing engineer at Synopsys, explains how the next generation DesignWare® Data Converter architecture uses digital calibration to deliver higher performance with up to 50% power and area savings compared to previous generations of data converters.

Translating real-world or “analog” signals to and from the digital domain has been a fundamental requirement in electronics since the days when the industry started to use digital logic. Data converters – both analog-to-digital converters (ADCs) and the reverse, digital-to-analog converters (DACs) – are the building blocks that enable designers to achieve this functionality.

Today, broadband communications is just one of the application areas demanding new levels of performance from data conversion IP (intellectual property). The need to digitize signals spanning tens or even hundreds of megahertz bandwidth means that the latest wireless and wireline communications standards require high-performance 10- to 12-bit ADCs with sampling rates of up to 250 mega-samples per second.

Like many of today’s other design challenges, meeting the performance requirements of data converters alone is not enough. Design teams want data converters that can deliver the performance needed at the lowest power and smallest area. Synopsys' development of the next generation of low power data converters enables designers to achieve the optimal balance between power, performance, and area.

New Pipeline Architectures
There are a number of established approaches to data converter design, each with their pros and cons. For example, Sigma-Delta converters handle narrow-band input signals and allow designers to employ oversampling and digital filtering to increase resolution. Nyquist rate¹ architectures are theoretically capable of digitizing signals with a bandwidth of up to half of the sampling rate. The pipeline architecture is the most flexible of all Nyquist rate ADCs, covering a very wide range of resolutions and sampling frequencies.

Synopsys’ new ultra-low power and compact DesignWare Data Converter IP uses a pipeline architecture approach with digital gain calibration. This combination is key to enabling significant improvements in power and area while achieving high performance.

Pipeline Data Converter
A pipeline ADC (Figure 1) consists of several cascaded, low-resolution stages, a flash ADC and a digital error-correction block that combines the outputs from all stages to obtain the high-resolution output code.

Figure 1
Figure 1: Pipeline ADC block diagram

Given certain input signal requirements, the sample-and-hold (S/H) function can be eliminated, in which case the first pipeline stage performs the sampling operation, which helps to reduce power dissipation.

Each pipeline stage is comprised of a low-resolution flash ADC and a multiplying digital-to-analog converter (MDAC), which is usually implemented as a switched capacitor amplifier. The flash ADC coarsely quantizes its input voltage and the MDAC determines the error made in that quantization (the residue). The MDAC output voltage (residue) is applied to the next stage for further quantization. This enables the digitization of the ADC’s input signal to be distributed across several low-resolution stages, allowing high resolution to be achieved at high sampling rates, with low power and area.

Analog Limitations
Power consumption increases proportionally with frequency, so as a data converter’s sampling frequency rises, so will its power. Higher resolution conversion typically requires amplifiers with larger gains, which are more complex and power-hungry.

Designers can add more amplifier stages to increase gain, or add extra amplifiers to control the gate voltages of the cascade transistors within the main amplifier. Both approaches make the design more complex, which makes it more difficult to compensate and ensure proper performance in all process, supply voltage and temperature (PVT) corners. Adding complexity increases power consumption and explains why technology scaling in analog circuits does not always help to reduce power consumption.

There are other trade-offs that designers must address in data converter design. Compensating for mismatches in components can necessitate the use of higher capacitances in the design of the converters, which can take more power to charge. Electrical noise also affects the design. If the design team needs to achieve higher resolution by reducing the effect of noise after having optimized the amplifier and the switches, they again need to increase the size of the capacitors, which presents yet another power-resolution design trade-off.

Optimizing Power and Resolution
Many analog design optimizations result in increased amplifier circuit complexity or necessitate the use of larger capacitors – both of which result in more power being consumed.

Mixed-signal integrated circuits have an inherent strength—the availability of ample digital computing performance. Fortunately, designers can use this to their advantage to overcome some of the constraints in the analog domain. Digital calibration enables the use of simple amplifiers and reduces the dependence on capacitor sizing to overcome component mismatches. The resulting data converter architecture is lower in power, robust against PVT variations, and scales more easily to advanced technology nodes.

Digital Calibration Circuitry
Digital gain calibration uses an MDAC with a gain error (Ge), followed by the backend ADC (where all the succeeding stages lie) as well as the functions inside the digital error-correction block that obtain the output code (Figure 2). The circuit calibrates the gain by multiplying the output of the backend ADC by 1/Ge, thus compensating in the digital domain for the (analog) gain error of the MDAC. The same principle can be extended to several MDAC stages in a nested fashion.

Figure 2
Figure 2: Digital gain calibration

The digital gain calibration also automatically calibrates the mismatches between capacitors within the amplifiers. Overcoming both the component mismatch and the finite gain of the amplifier allows the design team to use simpler amplifiers, thus significantly reducing power dissipation. While digital calibration does not reduce noise, use of simpler amplifiers does maximize the signal excursion, which relaxes the noise power specification of the MDAC stages for a given signal-to-noise ratio.

To be effective, digital calibration needs to generate accurate calibration values (1/Ge) in a timely manner, after the power-up of the circuit. Synopsys uses a combined approach—foreground calibration converges to the correct values as soon as the converter starts up and a background algorithm continuously adjusts the calibration values in response to any supply voltage or temperature variations happening during normal operation.

Lower Power, Higher Performance
The new generation of DesignWare pipeline data converters with digital calibration provides design teams with significant benefits. When compared with previous generation converters, they:

  • Use two to three times less power
  • Support much higher sampling rates
  • Occupy half the chip area
  • Benefit from technology scaling due to the substantial digital calibration block used

The ultra-low power and compact DesignWare Data Converter IP solutions consist of high-performance ADCs and DACs including:

  • 10-bit and 12-bit pipeline ADCs running up to 250 MSPS in single-channel and dual-channel configurations
  • 14-bit current steering DACs running up to 400 MSPS in single-channel and dual-channel configurations

¹ Nyquist rate architectures are those theoretically capable of digitizing signals with a bandwidth up to half of the sampling rate (fs/2).


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About the Author
Manuel Mota
Manuel Mota is a technical marketing manager for Data Converter IP within the Solutions Group at Synopsys, and has worked in Chipidea Microelectronica (Portugal) for more than 10 years in as analog IP designer. His responsibilities included the design of PLL and data conversion IP cores as well as complete analog front ends for communications. He later assumed the role of business developer for data conversion products with the responsibility of product definition and pre-sales technical engagement with customers. He joined Synopsys from MIPS Technologies in May 2009 as a technical marketing manager.

Manuel holds a PhD in electronic engineering from the Lisbon Technical University, which he completed while working at CERN (Switzerland) as a research fellow. He has authored several technical papers and presented in technical conferences on analog and mixed signal design.


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