Synopsys Insight Newsletter 

Insight Home | Previous Article | Next Article

Issue 4, 2012

Technology Update
Accelerate Software Development with High-Performance FPGA-based Prototyping

FPGA-based prototyping reduces the risk of SoC design teams missing their schedules. Neil Songcuan, senior product marketing manager at Synopsys, explains how Synopsys' next-generation HAPS®-70 FPGA-based prototyping solution is enabling faster pre-silicon software development, better system validation and improved hardware-software integration of IP and SoC designs.

Many design teams enjoy the benefits of using FPGAs for SoC prototyping. Growing pressure on chip delivery schedules and the economic penalties of being late to market or delivering a defective product are driving design teams to deploy FPGA-based prototyping more broadly. FPGA-based prototyping's ability to enable parallel hardware-software development, allowing system integration to begin months before SoC silicon is available, has encouraged design teams to use it for software development, hardware/software integration and system validation.

As businesses deploy FPGA-based prototyping more widely across their design teams, they are beginning to ask for more from their prototyping environments. In the past, many design teams developed their own prototyping boards in-house, often tailoring them toward the needs of each specific project. Today, reusability is a growing requirement, enabling the use of a common FPGA-based prototyping environment for different designs. Today, chip companies distribute their engineering resources globally, so having a common prototyping environment improves design team productivity. In addition, chip developers are constantly looking for ways to make the most efficient use of their engineers, and creating sophisticated SoC prototypes is often not deemed a core focus area.

These trends are compelling design teams to look for alternatives to their in-house prototyping environments.

HAPS 70: Sixth-Generation FPGA-based Prototyping System
Synopsys has developed its sixth-generation HAPS-70 series system to be more flexible and reusable than in-house or other commercially-available prototyping systems. The HAPS-70 systems take advantage of a scalable architecture and the latest generation Xilinx Virtex-7 2000T FPGAs to support a wide range of design sizes with capacities from 12 to 144 million ASIC gates. Synopsys engineers have focused on building a robust environment that reduces the risks for design teams looking to adopt and use FPGA-based prototyping across a range of projects. Key HAPS-70 features include:
  • Modular system architecture scales from 12 to 144 million ASIC gates to accommodate a range of design sizes, from individual IP blocks to processor sub-systems to complete SoCs
  • Enhanced HapsTrak 3 I/O connector technology with high speed time-domain multiplexing delivers up to 3x performance improvement in data throughput over traditional pin multiplexing
  • System definition and bring-up utilities speed hardware assembly and ensure the prototype's electro-mechanical integrity
  • Advanced power and cooling management
  • Improve debug efficiency with 100x greater visibility and 8x faster download time of debug trace buffer data
  • Advanced use modes including co-simulation, transaction-based verification, and hybrid prototyping

Providing a high-quality, reusable prototyping environment requires more than just hardware; Synopsys has enhanced its FPGA-based prototyping software tools – including its Certify® multi-FPGA prototyping environment and Identify® integrated debug tools – to take advantage of the new HAPS-70 hardware features.

Modular Symmetrical System Architecture
Synopsys has designed the HAPS-70 prototyping solution around a new symmetrical system architecture (SSA).

SSA defines the mechanical symmetry of the PCB and connector layout of the system, which enables design teams to use the HAPS-70 system in a modular way. The architecture ensures pin-to-pin forward compatibility for constraints, cables and daughter boards, which facilitates easy movement of the physical connections and complete prototyping designs. The architecture also specifies the use of connectors with delay-matched characteristics so that designers can move components with minimum delay to timing, which makes it easier to synchronize clocks across multiple FPGAs when scaling to larger systems.

The scalable architecture is key to providing flexible support for complex IP blocks and SoC designs alike. For example, design teams can take smaller designs targeting smaller HAPS systems and easily migrate them to larger HAPS systems that represent the entire SoC.

SSA ensures that design teams are no longer constrained to using just one, two or four FPGAs – they can connect multiple FPGAs to create large capacity systems –up to 144 million ASIC gates using 12 FPGAs. SSA enables design teams to take a bottom-up, ASIC-like approach to developing prototypes; reusing their subsystem and IP prototypes and ultimately saving system-on-chip bring-up time. For example, Figure 1 shows how HAPS-70 enables a design team to validate three separate subsystems – MIPI display, HDMI video and USB 3.0 – before combining them with the processor in the top-level configuration.

Figure 1: HAPS-70 symmetrical system architecture enables scalable prototyping
Figure 1: HAPS-70 symmetrical system architecture enables scalable prototyping

Synopsys Certify multi-FPGA design environment with HAPS system awareness supports and automates the hierarchical project flow, resulting in faster FPGA-based prototype bring-up.

Automated High-Speed Time-Domain Multiplexing
Even with today's high-capacity FPGAs, design teams frequently have to partition their largest SoC designs across multiple FPGAs in order to fit them into the prototyping system. The process of partitioning the chip creates another problem; passing sometimes thousands of signals between FPGAs.

Using pin multiplexing can be an effective way of squeezing multiple signals through a single off-chip connector. However, while solving one problem, pin multiplexing creates another –performance bottlenecks emerge as thousands of signals pass from one FPGA device to another.

The HAPS-70 system supports the automated insertion of high-speed time-domain multiplexing (HSTDM). HSTDM is a capability that is unique to the HAPS-70 FPGA-based prototyping system. HAPS' Certify software packs up signals and transmits them between FPGAs at over 1 Gbit/s. HSTDM is typically 3x faster than traditional pin-multiplexing solutions. Prototyping systems using HSTDM can run at near real-time speeds and handle data from real-world I/O.

Prototyping systems using HSTDM can run at near real-world speeds and handle data from real-world I/O.

Figure 2: HAPS-70 automates HSTDM
Figure 2: HAPS-70 automates HSTDM

HSTDM demonstrates the importance of tightly integrating hardware and software for the prototyping system, where Certify takes advantage of its knowledge of detailed timing information about the HAPS-70 system, connectors and cables, and enables customizations and optimizations not available with home grown hardware prototypes.

Figure 3: Enhanced HapsTrak 3 connector technology supports high-speed I/O interfaces
Figure 3: Enhanced HapsTrak 3 connector technology supports high-speed I/O interfaces

High-Speed UMRBus Interface
The capabilities in HAPS prototypes extend their usefulness across the entire product development organization, including the ASIC, software and systems development teams. And, HAPS integrates well into the broader design flow.

The enhanced HAPS-70 Universal Multi-Resource Bus (UMRBus) supports high-speed connectivity – up to 400 MB/s – between the HAPS prototyping environment and a host workstation. This high-performance, low-latency link enables the creation of hybrid prototypes, thanks to the efficient exchange of data between the HAPS system and a SystemC/TLM-based virtual prototype such as those based on Synopsys' Virtualizer™ tool set, which runs on the host (Figure 4). Using this kind of configuration, design teams can take advantage of advanced use modes, such as co-simulating hierarchical blocks using VCS® and other simulators as well as earlier software development with virtual prototypes. This approach allows the use of non-synthesizable verification IP, which can run on the host platform and be used to exercise the FPGA-based prototype.

Figure 4: Hybrid prototyping solution
Figure 4: Hybrid prototyping solution

High-speed connectivity to the host workstation is key to enabling remote access to the physical prototyping system, allowing remotely located designers to easily access registers and manipulate the HAPS-70 prototypes across their corporate network.

Easy-to-Use Integrated Software Flow
To prototype an ASIC design using FPGAs, the design team must convert certain design elements to structures that FPGA implementation tools can recognize. These elements, such as ASIC gate-level components or gated-clock tree structures, can be difficult and time-consuming to convert manually. The Certify software automatically recognizes and converts these ASIC-specific constructs into equivalent FPGA structures.

Certify enables automated (and manual) partitioning to support multi-FPGA implementation, to provide efficient conversion and partitioning of large ASIC designs onto HAPS multi-FPGA prototyping boards using a graphical user interface (GUI) flow guide.

Using the Synplify® Premier synthesis engine, Certify automatically maps ASIC-style RTL source code and DesignWare® IP to multiple FPGAs, providing immediate FPGA resource consumption feedback during the partitioning process.

The Certify software is tightly integrated into Synopsys' FPGA-based prototyping hardware and software flow. Board descriptions for HAPS systems are built into the Certify tool, allowing for immediate productivity with almost no setup time. Certify software assures optimal performance because it automatically takes advantage of HAPS signals to provide HSTDM, which ensures the fastest available connections between FPGAs.

Advanced Debug
Gone are the days of using logic analyzers to debug FPGA hardware. Now FPGA vendors provide embedded probes to view activity at the post-synthesis gate-level. Multi-FPGA prototypes make the debug problem harder because design elements can be split across devices following implementation at the gate level. Design teams can be more productive if they are able to drive debug from the comfort of their familiar RTL.

The HAPS-70 system integrates with Identify software to support multiple debug capabilities that help designers locate bugs quickly and efficiently. The HAPS Aware Identify debug features provide simulator-like visibility of the prototyping project at the RTL source level. Designers can take advantage of multi-FPGA debug visibility to debug their prototypes regardless of the design partitioning and benefit from simulator-like signal browsing.

Identify's Deep Trace Debug enhanced visibility gives users as much as 100x additional design visibility by utilizing off-chip, external memory storage. Sample results are available quickly over the high-performance HAPS UMRBus Interface Pod link between the debugger workstation and the HAPS-70 system.

Identify also supports the following advanced debug features:
  • Ability to instrument and debug an advanced FPGA design directly from RTL source code
  • Advanced trigger creation allows the viewing of desired design operation scenarios and the ability to probe specific nodes in the circuit
  • Visibility into the internal design while operating at full speed
  • Display of debug results superimposed on top of RTL source, RTL structural view, or with a waveform viewer
  • Instrument an FPGA-based ASIC prototype prior to device partitioning and planning

Summary
Synopsys' HAPS-70 Series prototyping systems help design teams maximize their design productivity by providing a high-performance, scalable FPGA-based prototyping solution that can be used across multiple projects and engineering locations. The HAPS-70's symmetrical system architecture enables designers to create prototypes of up to 144 million ASIC gates, using a modular approach that supports hierarchical assembly of high-capacity prototypes from their constituent subsystems.

Automated HSTDM yields a 3x higher performance compared to traditional pin-multiplexing methods, which increases interconnect bandwidth and enables HAPS-70 based systems to run at near real-world speeds using data from near real-world I/O.

The hardware and software features that combine to make up the HAPS-70 prototyping system enable design teams to create scalable, high-performance and reusable prototypes for use earlier in the design cycle. Deploying FPGA-based prototypes for earlier software development, hardware/software integration and system validation is helping design teams build next generation designs faster, with less risk and more profitability.


More Information
HAPS system overview

HAPS Deep Trace Debug

HAPS-70 News Release


About the Author
Neil Songcuan is a senior product marketing manager, who is responsible for the FPGA-based Prototyping Solution at Synopsys. His experience includes the areas of semiconductor, hardware-assisted verification and system validation. Neil has held various marketing management positions with Synplicity, Mentor Graphics and IKOS Systems. Additionally, Neil worked in customer marketing and application engineering roles with Altera Corporation. Neil holds a B.S. degree in Electrical Engineering from San Jose State University.


Having read this article, will you take a moment to let us know how informative the article was to you.
Exceptionally informative (I emailed the article to a friend)
Very informative
Informative
Somewhat informative
Not at all informative