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Issue 2, 2011
Accelerate Design by Exploring Early RTL and Constraints
RTL development involves lengthy iterations of synthesis and refinements to the RTL and constraints, a major risk to project schedules. Chris Allsup, Synopsys, introduces Synopsys DC Explorer, which helps designers reduce the time it takes to produce a better starting point for RTL synthesis.
Chip companies face growing pressure to bring increasingly complex products to market faster. As a consequence, design teams are striving to get more design done in less time, and are looking for ways to become more productive.
Designers are “Locked-In” Too Early
The task of developing new RTL code and integrating it with legacy blocks and dozens of third-party IP is time-consuming. Designers must wait until their RTL and constraints are sufficiently complete to perform initial RTL synthesis runs that will give them the much-needed insight into the timing, power and area of their designs. Typically, multiple iterations of synthesis and refinements to the RTL and constraints are needed to arrive at a “clean” design.
Since the architecture is effectively “locked-in” by the time synthesis can be performed, designs often turn out to be sub-optimal heading into synthesis and place-and-route. It is not feasible to meet the design goals without major iterations downstream in the flow or, in some situations, without going back and making significant modifications to the RTL itself.
Early RTL Exploration is Needed
Designers therefore need the ability to efficiently explore the RTL and constraints and perform rapid what-if analyses to better manage risk and accelerate the entire design implementation flow.
To meet this need, earlier this year Synopsys introduced a new product, DC Explorer. It represents an evolutionary step in design implementation because of new technology that makes it tolerant of incomplete design data, faster than RTL synthesis and tightly correlated with Design Compiler®. These capabilities enable efficient exploration of the RTL and constraints in the early development phase of the design cycle and creation of a better starting point for RTL synthesis (Figure 1).
Figure 1: Developing the RTL and constraints with and without early RTL exploration
DC Explorer has built-in tolerance of incomplete design data so that users can explore the design, identify data inconsistencies and generate a netlist for physical exploration, even while the data is still being developed. With runtimes that are 5-10X faster than RTL synthesis, designers can perform quick what-if analyses to identify and improve the design before synthesis. And since DC Explorer has 10% timing and area correlation with DC Ultra™ using Topographical technology, it provides unprecedented visibility into implementation results very early in the design cycle. Let’s now take a closer look at these capabilities.
Designers Want Feedback on Incomplete or Inconsistent Design Data
Early in the design cycle the RTL is still incomplete, so the design has a variety of data inconsistencies such as inconsistent clock definitions and interface width mismatches, as well as a number of infeasible timing paths. (Figure 2).
Figure 2: RTL and constraints are incomplete in the early stages of design
DC Explorer has built-in tolerance for incomplete or inconsistent design data, essential to providing feedback on early RTL code. First, it produces detailed reports on design discrepancies such as bus port mismatches and bus width inconsistencies so the designer can make corrections prior to synthesis. This speeds-up the creation of a “clean” design dataset.
Second, despite incomplete design data, DC Explorer generates a usable netlist for physical exploration. In a traditional flow, physical exploration must wait for RTL synthesis, but with RTL exploration, designers can get a head-start on the floorplanning task (Figure 3). The netlist generated by DC Explorer lets the design team explore different floorplans earlier in the design cycle, prior to synthesis, which helps them to determine how different physical constraints can impact the timing and routability of the design. Enabling designers to thoroughly explore their initial designs reduces unexpected iterations late in the design cycle.
Figure 3: DC Explorer generates a usable netlist that lets designers begin physical exploration earlier
Designers Want Faster Runtimes to Boost Productivity
Longer runtimes discourage the use of technology for doing “what-if” analysis. In the early stages of a design, design teams want to use tools that are easy to deploy, compatible with existing scripts and flows for synthesis, and offer rapid turnaround times. To be effective, an environment for design exploration should allow designers to refine their RTL several times each day.
DC Explorer runs 5-10X faster than full RTL synthesis, based on optimized technology that accelerates runtimes independently of the quality of the design constraints. Furthermore, DC Explorer supports multicore compute platforms. Using a four-core platform, for example, can provide a further 2X speedup over a single-core processor.
Designers Need Accuracy, Even at an Early Stage
Providing designers with earlier visibility into quality of results (QoR) is only useful if the design team can trust the information. An RTL exploration solution must correlate with actual synthesis results for designers to be able to determine in advance if their designs will likely meet the required timing, area, power and floorplan goals.
Timing and area data from DC Explorer correlate to within 10% of Design Compiler results (Figures 4 and 5). Because DC Explorer is compatible with DC Ultra, it is easy to deploy in existing Synopsys-based flows. Both tools share the same scripts so DC Explorer can extract the information it needs quickly and efficiently. DC Explorer generates easy-to-navigate, HTML-based timing reports to help designers identify problematic and infeasible timing paths.
Figure 4: DC Explorer timing results are within 10% of DC Ultra (Topographical)
Figure 5: DC Explorer area results are within 10% of DC Ultra (Topographical)
Design teams need to explore RTL earlier if they are to achieve faster design schedules for “gigascale” systems-on-chip. DC Explorer has built-in tolerance of incomplete design data so that users can explore the design, identify data inconsistencies and generate a netlist for physical exploration, even while the design team is still developing the data. DC Explorer runtimes are 5-10X faster than full RTL synthesis, so designers can perform quick what-if analyses to identify opportunities to improve the design before embarking on full synthesis. And, since DC Explorer has 10% timing and area correlation with DC Ultra (Topographical), it provides unprecedented visibility into implementation results very early in the design cycle.
DC Explorer completes the picture of exploration across Synopsys’ Galaxy™ Implementation Platform. With exploration throughout Galaxy, designers can begin the next implementation task in the flow—whether it’s RTL synthesis, design planning or block implementation—much earlier, before they complete the current task. This leads to greater design concurrency throughout the flow, saving time and reducing unexpected iterations late in the design cycle.
Download the DC Explorer datasheet:
- Watch the DC Explorer videos:
About the author
Chris Allsup, marketing manager in Synopsys’ synthesis and test group, has more than 20 years combined experience in IC design, field applications, sales and marketing. He earned a BSEE degree from UC San Diego and an MBA degree from Santa Clara University. Chris is a member of IEEE Computer Society and has authored numerous articles and papers on design and test.