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Issue 2, 2012
The Best of Both Worlds for SoC Prototyping
Synopsys’ Hybrid Prototyping is the first complete, commercially available SoC design prototyping solution to seamlessly integrate virtual and FPGA-based prototyping environments. Troy Scott, Synopsys, explains how bringing the two together gives design teams the best of both worlds.
Design teams who validate complex system-on-chip (SoC) designs typically call upon two different prototyping methods: virtual prototypes using SystemC™ before RTL is available, and hardware-based prototypes using FPGAs once they have designed the hardware and created the RTL code.
Each of these prototyping techniques have their pros and cons and work well as standalone methods. However, by linking the two approaches, design teams can dramatically reduce bring-up time and effort.
The Benefits of Parallel Development
Software has become the critical path for SoC-based product development. Traditionally, design teams have had no choice but to wait until hardware became available before writing and testing code. This sequential process of designing hardware then software is both slow and risky: if any system-level issues come to light as a result of the software becoming available, it is often too late to make significant changes to the hardware to address them.
In order to reduce time-to-market, design teams must start developing software before the hardware becomes available, which means developing hardware and software in parallel. Advanced SoC prototyping techniques enable a parallel development methodology, which helps design teams reduce time-to-market and improve product quality.
Virtual Prototyping for Software Development – Before Hardware
Virtual prototypes are fast, fully functional software models of systems under development that execute unmodified production code and enable developers to debug and analyze designs quickly. Virtual prototypes use loosely timed transaction-level models (TLMs) written in SystemC, which run on a host workstation.
Many SoC blocks are easier and faster to create using SystemC than RTL. For example, design teams can create loosely timed models of processor cores, memory caches, and display controllers far faster than they can create the equivalent RTL. In addition, TLMs for many common SoC design blocks, such as interfaces and processors, are readily available in the market as IP vendors increasingly deliver SystemC models alongside the IP itself. These models have better throughput than a live hardware prototype.
Design teams can use virtual prototyping to develop code before RTL is available, easing the effort to integrate software with the hardware. The deep visibility into register and memory states available in a virtual environment enables unparalleled debug efficiency, helping design teams improve design quality and reduce the effort needed to complete system validation.
FPGA-Based Prototyping for Cycle-Accurate Validation
Some SoC blocks are easier to validate using real, cycle-accurate FPGA-based hardware. For example, real-world IO connections help ensure a radio interface, like Bluetooth, operates correctly. Some hardware execution engines also require the high performance and cycle accuracy that is only possible with actual hardware.
FPGA-based prototyping enables design teams to quickly create ASIC prototypes with high-speed hardware prototyping systems. The prototyping flow includes software conversion of ASIC RTL into one or more FPGAs. FPGA-based prototypes provide cycle-accurate, high-performance execution, and real-world interface connectivity before test chips tape out.
Hybrid Prototyping Solution
Synopsys’ Hybrid Prototyping solution (Figure 1) is the industry’s first integrated hybrid prototyping solution for SoC designs. It blends the strengths of Synopsys’ Virtualizer™ virtual prototyping environment and HAPS® FPGA-based prototyping environment to enable software development and system integration much sooner in the project lifecycle. This configuration also gives design teams the best of both prototyping worlds in an environment that delivers optimal performance and capacity.
A hybrid prototype provides design teams with more freedom to integrate high-performance processor models, Synopsys DesignWare® IP and real-world IO. They can freely partition between virtual and FPGA-based environments, enabling them to create prototypes of their SoC earlier in the project lifecycle by mixing the block representations most readily available for each prototype environment. For example, abstract models representing pre-RTL design blocks can reside in the virtual prototype and interact with existing ASIC RTL residing in the FPGA-based prototype.
Figure 1: Synopsys Hybrid Prototyping Solution
High-Performance Data Exchange
Synopsys’ Hybrid Prototyping Solution incorporates the hardware and software data exchange components required to connect a virtual prototype to an FPGA-based prototype. This eliminates the engineering effort needed to design and qualify data exchange methods that link the SystemC/TLM-based prototyping environments to FPGA-based prototyping systems.
The data exchange uses a low-latency physical link, the UMRBus, and AMBA® bus transactors to communicate between the virtual and hardware prototypes.
The pre-validated AMBA transactor library includes the resources for both prototyping domains: C++ or SystemC/TLM 2.0 for virtual prototypes and synthesizable Verilog for the FPGA-based prototyping system. To ease physical connections, the HAPS UMRBus interface kit provides a PCI Express peripheral card for the host workstation and an interface pod for the HAPS system.
The AMBA transactor library converts between TLM events and hardware-level signal activity. The design team can configure transaction buffering and clock synchronization, choosing to synchronize prototype operation for easier troubleshooting, or decoupling for best system speed.
Use Case Example: Mobile Applications Processor
In the case of a mobile applications processor (Figure 2), all of the blocks could target either a virtual prototype or an FPGA-based prototype, but the modeling and integration effort can vary dramatically depending on the environment chosen for the block. Design teams should consider the attributes of each block, including capacity, development speed and real-world IO access needs. All of these can constrain or limit the degree of hardware and software development that the design team can accomplish.
Figure 2: Partitioning a mobile applications processor for virtual and FPGA-based prototypes
The ARM processors, level 1 and 2 cache memories (L1, L2), and the display block are good candidates for transaction-level models since they are easier and quicker to obtain than RTL and have excellent throughput for software execution. These blocks are ideal for implementation in a virtual prototype.
On the other hand, some of the peripherals, such as the graphics engine and the radio interfaces for BT, GPS, and WiFi, lend themselves to prototyping in an FPGA-based system where test patterns and analog PHYs are easier to connect in order to validate the design.
Design teams can have more realistic and complete SoC prototypes sooner in the project by adopting hybrid prototyping.
Synopsys’ complete Hybrid Prototyping solution integrates high-performance processor models, a pre-validated library of transactors for AMBA-based designs, DesignWare IP, transaction-level models and real-world IOs.
Design teams can partition an SoC design between a Virtualizer-based virtual environment and HAPS FPGA-based environment for optimal performance and capacity. By mixing the two environments, design teams quickly gain access to a more complete prototype.
- For design teams already using virtual prototypes, adding FPGA-based prototyping enables:
- reduced modeling effort by bringing in existing RTL, IP or subsystem earlier
- faster integration of real-world IO devices
- higher performance utilizing HAPS to model cycle-accurate hardware execution engines
- For design teams already using FPGA-based prototypes, adding virtual prototyping enables:
- earlier bring-up by starting prototype development before all the RTL is available
- faster execution by utilizing high-performance CPU models
- greater debug visibility of software under development
- easier validation of IP in SoC context for IP developers
- More Information:
About the Author
Troy Scott, product marketing manager, is responsible for FPGA-based prototyping software tools at Synopsys. He has 20 years of experience in the EDA and semiconductor industry. Before joining Synopsys he was a product manager at Lattice Semiconductor, where worked to design and market FPGA design tools. His background includes HDL synthesis and simulation, SoC prototyping, and IP evaluation and marketing. He holds a BSCE from Oregon Institute of Technology and a Graduate Certificate in Computer Architecture and Design from Portland State University.