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Issue 2, 2013

Technology Update
ProtoLink™ – The Innovative Simulation-Like Debug Solution for Multi-FPGA SoC Prototype Systems

The complexity of modern SoC designs requires a more comprehensive verification methodology. Verification must work at all levels, from a virtual platform to RTL simulation, emulation and FPGA-based prototyping. The importance of FPGA-based prototyping is also increasing because it is usually the first time real software and/or external interfaces can be run with hardware in an environment fast enough to predict real-world results.

The FPGA-Based Prototyping Methodology Manual (FPMM) is a comprehensive and practical guide to using FPGAs as a platform for SoC development and verification.

A complex SoC is usually hard to map to only one FPGA, despite the fact that FPGA devices are getting larger. The multi-FPGA prototype system is often needed to encompass the design, but it is increasingly difficult to set up and debug these systems. There are also many different considerations when choosing the right FPGA-based prototyping system. Choosing a system may be somewhat subjective depending on, for example, the purpose of the prototyping usage, the SoC design itself, and the customers’ available resources. The implementation flow can also be different for different designs. For example, the design partition for a multi-FPGA board can be done pre-synthesis or post-synthesis depending on performance requirements, design style and available interconnections on the board.

After dealing with these setup issues, debug is the key to make the chosen FPGA-based prototype run effectively. As mentioned earlier, usually an FPGA-based prototype is initially used to test the design with some real software or external interfaces at a higher speed than it has been tested before. As a result, some problems are expected even though the design has passed many tests beforehand. However, it is very difficult to debug a multi-FPGA prototype system with traditional debug methods because the viewable signals and depth are usually not enough to identify the root cause of an error. Seeing the additional signals that could assist the debug process may require rerunning the entire setup process, which is long and unpractical.

A debug solution that can address these challenges must also support a variety of FPGA-based prototyping systems so the same debug methodology can be used consistently, thereby easing the learning process.

ProtoLink: Simulator-Like Debugging for Multi-FPGA Prototype Systems
ProtoLink was designed with “openness” in mind. It is an innovative, simulation-like multi-FPGA debug solution that combines IP, interface hardware and debug software into a single user environment, offering simulator-like visibility and a fast debug turnaround.

ProtoLink works with both HAPS® FPGA-based prototyping systems and custom FPGA prototype boards. It is also integrated with commonly used FPGA implementation tools so that ProtoLink can be adopted without changing the existing implementation flow.

One of the innovative concepts in ProtoLink is an external interface card that interfaces with both a workstation and the prototype board. This offers many benefits, including:
  • Minimal debug hardware needed on each FPGA. Based on users’ real data, the area overhead is only around 1% on the Xilinx XC5VLX330 device. For larger devices, like a V6 or V7, the area overhead is less than 1%.
  • ProtoLink can easily connect to the majority of commercially available FPGAs. The values of the observed signals on each FPGA are transported to the ProtoLink interface card by a universal cable connection. As long as the FPGA has the required pins/connectors to connect with the cable, different prototype boards are treated the same way by ProtoLink.
  • ProtoLink can treat signals from different FPGAs, or even boards, as if they were coming from a single source. The ProtoLink interface card includes a programmable FPGA that processes and consolidates all the data and handles runtime events/triggers. So ProtoLink is a true multi-FPGA debug solution and a user can use any signal from any FPGA to setup events/triggers.
  • ProtoLink can capture thousands of signals in two seconds of emulation time. Over time, the current 4GB/8GB memory can save millions of cycles so users don’t need to worry about finding the correct trigger near the bugs, as they would if they had the much smaller probe memory found in traditional debug methods.

The picture of ProtoLink components and their connections are shown in Figure 1 below.

Figure 1: ProtoLink components and connections

Probe ECO for Fast Debug Turnaround Time
Another key innovative concept of ProtoLink is its use of software to establish the correlation between RTL and the gate level without changing the existing implementation flow.

To achieve simulator-like visibility and fast debug turnaround time, users must be able to see the value of any signal at the time they want. This is almost impossible in the FPGA world because users must predefine the signals they want to see before the set-up process is complete. After that, users lose track of the RTL signals and can only see the synthesized netlist and place-and-route (P&R) netlist with unknown gate-level names. That is why most traditional FPGA debug tools require rerunning the setup flow to see additional new signals. That has been the only way to guarantee that the correct RTL signals will be pulled out and observed.

ProtoLink establishes a much smarter RTL/gate correlation. When users want to see additional signals, the ProtoLink Probe ECO feature will find the corresponding signal names in a P&R netlist and do a partial routing for users so that the new signals are available. This enables users to see new signals in minutes without restarting the entire flow – a process that usually takes several hours. It also enables users to easily set up new signal events and triggers at runtime.

Imagine you can see a very large window for many cycles with many signals and can also see any signal you would like to see at the time you need. This will greatly improve your debug turnaround time and give you the capability to complete multiple debug iterations in one day.

Simulator-Like Design Control
For simulator-like design control on a prototype board, force and release is a must-have capability. This unique feature is available for Xilinx FPGAs through ProtoLink’s add-on Full Visibility (FV) module.

With this unique feature, users can control design modes, do what-if analysis and even run fast fault simulation at runtime. It eliminates the need to rerun a long set-up flow and can greatly expand the number of verification tasks that the prototype board can handle.

The ProtoLink FV module can also provide cycle-by-cycle or snapshot dumping for all registers/memory outputs to further expand visibility into the design.

ProtoLink: Part of the Verdi3™ Open Debug Platform
Using the single compiler technology, ProtoLink and Verdi3 can run seamlessly. ProtoLink can use all Verdi3 debug features when debugging the FPGA prototype board. The values of signals that can do probe ECO are annotated directly on Verdi3 source code. During the Verdi3 debug session, users can easily drag and drop the signals of interest into the ProtoLink software to run Probe ECO. Within a few minutes, a new bin file will be generated that can download to the prototype board to run again and get the values of the interested signals. This new debug process can greatly reduce prototype debug time and accelerate prototype board verification as shown in Figure 2.

Figure 2: Cut debug time in half and accelerate prototype verification

Based on user feedback, ProtoLink can always find and fix any prototype bug within one week. With this predictable debug time, users can move more verification tasks to the prototype board. The open architecture, simulator-like visibility and controllability, and fast debug times can help users to apply the same debug methodology across prototype boards and leverage newer FPGA and prototype boards sooner.

More Information

About the Author
Howard Mao is Product Marketing Director at Synopsys and has over 20 years of experience in the EDA industry. Previously, at SpringSoft and Mentor Graphics, he held various roles in technical support, sales/marketing, general management and led several R&D projects. He also had several years IC design experience before joining the EDA industry. Howard earned both M.S. and B.S. degrees in Electronic Engineering from the National Chiao-Tung University in Hsinchu Taiwan.

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