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Issue 4, 2012

Technology Update
The Past, Present and Future of DDR4 Memory Interfaces

The latest DDR4 SDRAM memory standard offers significant performance benefits for SoC designers. Graham Allan, senior product marketing manager for DDR at Synopsys, discusses some of the challenges that design teams face in making the change from DDR3.

DDR4 SDRAM is the latest JEDEC standard for commodity DRAM. It supports a higher range of data transfer rates and lower voltages than previous standards. While JEDEC has specified this latest standard primarily with servers, PCs and laptops in mind, we anticipate manufacturers to favor DDR4 for some portable embedded products, such as tablets. In the long term, DDR4 will be significantly less expensive than specialty low-power memories, such as LPDDR2 and LPDDR3, and will waterfall into mobile applications where the form factor and battery allow.


Overcoming DDR4 Technical Challenges
DDR4 has had a long gestation, taking seven years to standardize within the JEDEC memory standard committees. The technical challenges facing DDR4 have been significant, primarily because the standard must support very high data rates – up to 230 Gbps of maximum bandwidth for a 72-bit wide data bus. DDR4 has approximately 20 new features and as a result is more complex than the previous standard, DDR3. Because of its complexity, DDR4 SDRAM products come to market later than expected, but we expect compatible SDRAMs to start shipping in volume next year.

We have been working with JEDEC for some time to enable us to launch our memory interface IP to coincide with the increase in market demand for DDR4. To meet this schedule, we started to develop DDR4-compatible products before the standard was actually finalized.

In the past, creating a DDR memory interface was an in-house design task of significant complexity. The design team would have to procure a memory controller, assemble the IP components to create a PHY, source I/Os and a PLL from various IP vendors, and then integrate, test and achieve timing closure for the logic and layout. As the DDR data rates increased with DDR2 and DDR3, achieving timing closure without a hard solution for the PHY became more and more difficult using a standard ASIC flow. Design teams quickly recognized the benefits of being able to source a complete, integrated, tested and compliant memory interface solution, incorporating a hard PHY, from a single vendor. Synopsys recognized that offering an integrated DDR memory interface solution would enable design teams to focus their engineering efforts on tasks that added differentiated value to their designs.

We have continued to support a broad range of process technologies with our hard DDR PHY solution, offering an off-the-shelf product that design teams can use with a minimum amount of engineering effort. As a result, Synopsys is a DDR IP market leader with over 330 design wins for its DDR PHYs and controllers.

Easing the Transition from DDR3 to DDR4
When a design team is faced with the transition to a new standard, it is imperative that they minimize the risks involved in making that step. One way that Synopsys supports technology transitions is by creating flexible IP that is backward-compatible. Synopsys DesignWare® DDR4 IP is compatible with DDR3 memory. In fact, the Synopsys DDR4 IP is also compatible with LPDDR2 and LPDDR3 memories that primarily target mobile applications such as smartphones. This enables design teams to use the same, familiar DDR memory interface with low-power memory, and take advantage of cheaper, faster DDR4 memory for applications that don't justify the extra investment in low-power memory. By supporting DDR4, DDR3 and LPDDR2/3 in a single IP product, the DesignWare DDR solution enables designers to interface with either high-performance or low-power SDRAMs in the same SoC, which is a key requirement of applications processors for smartphones and tablets.

Figure 1: Synopsys DesignWare DDR Memory Interface IP architecture
Figure 1: Synopsys DesignWare DDR Memory Interface IP architecture

In order to facilitate interoperability between internally developed controllers or PHYs, a standard DFI 3.1 interface connects the memory controller and PHY for maximum flexibility.

DDR4 introduces some subtle restrictions with new timing parameters, which can affect performance if the design team doesn't account for them. It also incorporates more features than DDR3, including data bus inversion (DBI), an idea borrowed from the Intel P4 front-side bus. Due to the new VDDQ termination, the DDR4 data bits consume a maximum amount of power if they are driven low and none if they are driven high. DBI limits how many signals can be driven low at any one time to avoid a worst-case power situation. DBI also provides a performance benefit since it reduces Synchronously Switching Output (SSO) noise by limiting the number of data bits that can switch at the same time during any given cycle.

Maintaining DDR Signal Integrity
One of the challenges when designing a DDR memory interface is that there are no standards for the memory controller or the physical channel – all we have to reference is the specification for the DRAM itself. That is in contrast to other interfaces, like USB and PCI Express, and other leading serial interface protocols. Without a specification, design teams don't necessarily know exactly what they should be paying attention to when they integrate the IP, and that can lead to problems at extremely high data rates. Signal integrity problems can emerge because the board design isn't quite right, or there are insufficient power and ground connections on the chip, or any combination of issues.

Our experience of working with high-performance designs, primarily as a result of providing hard PHYs over a number of years, enables our IP and design services to recognize and address signal integrity issues. We offer a signal integrity report service, which was created to fit in with customer design reviews, to help identify potential issues. We can help to analyze timing issues and take corrective action before the design team commits the design to hardware.

Improving DDR4 Performance and Utilization
We have designed the DDR4 multiPHY Memory Interface with built-in system monitoring and control. By monitoring traffic patterns, the IP can selectively shut down elements of the IP, which reduces power consumption and prolongs battery life.

The DesignWare DDR4 IP is designed for 28-nanometer (nm) processes and beyond. Moving to faster processes enables the use of fewer pipeline stages, which, along with some changes in functionality, helped us to achieve up to 50% lower latency than the DDR3 generation of designs.

One of the key tasks for the memory controller is to optimize execution of the commands queuing at each of the input ports. Like controlling the traffic at a multi-way intersection, the memory controller is like a traffic cop – it decides which "car" to let through first, preventing each queue from backing up too much, allowing emergency vehicles to take priority, and ensuring that the traffic flows as smoothly and efficiently as possible.

To control traffic, most of the memory controllers on the market use a FIFO for each bank of the SDRAM array. However, FIFOs have a fundamental constraint ‒ they can only see the instruction at the head of each queue. The DesignWare DDR4 Memory Controller uses content-addressable memory (CAM) to optimize the scheduling of the memory access commands. The CAM can see the contents of the queue beyond the first instruction. As a result, this unique CAM-based DDR controller can optimize the scheduling of data read/write traffic from multiple hosts, maximizing performance, minimizing latency and improving utilization of the maximum theoretical bandwidth of the interface.

Looking to the Future of DDR4
It's a common misconception that DDR4 memory will support its maximum 3200 Mbps data rate from the start. In fact, the current DDR4 JEDEC standard and planned memory vendor offerings only cover DDR4 SDRAMs up to 2400Mbps. The DDR4 SDRAM roadmap supports a transition to higher data rates and lower costs, culminating in memories offering twice the performance of the current generation of DDR3 designs, but this will be a progressive release of higher performance products over several years. Synopsys will develop higher-performance hard PHYs to handle the greater data rates in line with this roadmap.

Beyond DDR4, the industry is getting to the end of the line of what can be achieved using wide parallel interfaces to SDRAM. Having large numbers of parallel pins presents a growing connectivity challenge between application processors and memory chips sitting side-by-side on a board. These challenges manifest themselves in routing congestion, signal integrity issues, pad-limited designs, increased power consumption and manufacturing expense.

Consensus opinion points to the use of stacked die and through-silicon vias (TSVs) as a future solution to the problem of connecting massively parallel interfaces.

Stacking devices in one package makes a large number of connections available without having to pin out the I/O and connect it through the PCB. Stacking opens up the possibility of having thousands of connections, enabling slower but wider interfaces that deliver even more bandwidth. Although these technologies are beginning to emerge, it will be another five to ten years before this technology matures sufficiently to become economically viable, although some commentators believe the maturation will be faster.

"Synopsys' support for DDR4 memory is an important contribution to building a robust DDR4 ecosystem. DDR4 brings substantial power and performance benefits to the industry, and Micron is aggressively driving its introduction. By implementing its DesignWare DDR Interface IP with backward compatibility in mind, Synopsys is enabling chip developers to bridge the transition from today's DDR3-based SoCs to the upcoming DDR4 designs."

Robert Feurle, vice president of DRAM marketing for Micron Technology, Inc.

More Information
Synopsys DesignWare DDR Memory Interface IP

About the Author
Graham Allan joined Synopsys in June 2007. Prior to joining Synopsys, Mr. Allan was with MOSAID Technologies as director of marketing for Semiconductor IP. With over 23 years of experience in the memory industry, Mr. Allan has spoken at numerous industry conferences and represents Synopsys at the JEDEC Memory standards committees. A significant contributor to the SDRAM, DDR and DDR2 memory standards, Mr. Allan currently holds 16 issued patents in the area of DRAM design.

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