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Issue 1, 2012
A Silicon Interposer-based 2.5D-IC Design Flow, Going 3D by Evolution Rather than by Revolution
Dr. Michael Jackson, VP of R&D and Physical Implementation at Synopsys ponders the 3D-IC technology trends, their timeline, and the impact on EDA, proposing that a silicon interposer-based 2.5D-IC design flow is well within our reach. This article is based on a presentation given by Dr. Jackson at the 2011 3D Architectures for Semiconductor Integration and Packaging Conference.
Technology Trends and Timeline
More than 2D-IC technology trends and their timeline are critical to drive the EDA roadmap, as blind investments too often lead to dead ends. Today, as far as the mainstream is concerned, there are four main categories of more than 2D-IC emerging, “sorted” by time of probable volume production: memory “cubes”, silicon interposers, memory on logic, and true 3D stacks. Performance, cost, heat management, and supply chain are key metrics to be considered.
Memory cubes, NAND FLASH or DRAM, are stacks of identical tiers with a relatively small number of through-silicon vias (TSVs) with no need for redistribution layers (RDL). Figures 1 and 2 show two examples of memory “cubes”. Figure 1 shows a 16-gigabit memory device composed of eight stacked, 50-micron-thick, 2-gigabit NAND flash die which are a combined 0.56-millimeter in height. The stacked device shows a 15% smaller footprint and is 30% thinner than an equivalent wire-bonded solution. Wafer scale packaging (WSP) also reduces the interconnect length, resulting in an approximately 30% increase in performance due to reduced electrical resistance. Figure 2 shows the die photo of the recently announced Micron DRAM Hybrid Memory Cube (HMC). The memory die stack seats on top of a small logic die, which takes care of buffering and routing from/to the memory banks. The HMC delivers 15X higher bandwidth vs. DDR3 (120 GBps) using 70% less power in one-tenth the silicon real estate of existing technologies. The current forecast is to see memory “cube” technology in server and networking markets as early as 2012, with significant volumes in 2013.
Figure 1: Memory "Cube"
Figure 2: Hybrid Memory "Cube"
TSVs are only needed on the silicon interposer, thus minimizing the extra costs of advanced logic and wafer thinning challenges. Figure 3 shows an example of a silicon interposer: a SEM cross-section of Xilinx Virtex 7, which is made of multiple slices (die) of FPGA (TSMC 28nm HPL, 6.8B transistors) stacked onto a passive silicon interposer (TSMC 65nm, 4 layers of metal). Only the silicon interposer, which is manufactured using a mature 65nm process, goes through TSV drilling/etching and wafer thinning/back-grinding. With features 100-1000x smaller at 65nm than the package substrate ones, silicon interposers allow for orders-of-magnitude bigger connectivity, dramatically reducing latency, and power consumption. Silicon interposers are sampling now, and the current forecast is to see volume production in the second half of 2012.
Figure 3: Advanced Logic onto Silicon Interposer
Memory on Logic
Memory on logic delivers higher bandwidth, thus boosting performance. Cost and heat management are the challenges. Figure 4 shows an example of memory on logic: a wide I/O memory “cube” on logic, where the dashed light blue area represents the wide I/O memory “cube” stacked onto the advanced logic die, front-to-back (F2B). The red area highlights the silicon real estate occupied by the TSV, µbumps, and by the memory controllers. Both the wide I/O memory “cube” and the logic chip have thermal sensors (represented by green squares) to assess if the logic chip is creating hot spots and where, to determine the appropriate self-refresh rate for the DRAM. Wide I/O SDRAM JEDEC standardization is on-going and should be published in early 2012; the current forecast is to see the first wide I/O SDRAM “cubes” in late 2012 or 2013, and the first products in late 2014 or 2015.
Figure 4: Memory “Cube” on Advanced Logic
True 3D Stacks
Some engineers are wondering whether true 3D stacks may represent a technically and economically viable alternative to scaling while others believe that it may complement scaling to boost integration and performance to unprecedented levels. Real, published examples of 3D stacks for the mainstream are not available yet; cost, heat management, and supply chain are the challenges. The cost of TSV manufacturing is still too high for most applications. In a 5µ diameter, 10:1 aspect ratio via middle TSV process technology, each tier (i.e., each wafer) bears an extra cost of $80-100, or 2-3%; the enabling point of 2.5D- and 3D-IC is very application- and design-dependent. The power/heat management burden is an unresolved challenge. Delayed payment and inventory management are major supply chain hurdles for involved parties to overcome. The current forecast is to see the first products in the second half of this decade.
In summary, 3D-IC integration is certainly warming up, but not all applications are at the same stage of maturity, the runway is still very long, and silicon interposers may represent an acceptable solution for a number of applications.
Impact on EDA
The Synopsys effort starts long before IC design at the TCAD level. 3D stacks incorporate different materials, often bonded together, with varying coefficients of thermal expansion (CTE). Any temperature change leads to compressive and tensile stresses in the materials due to the thermal mismatch. The induced stresses lead to silicon deformation, which changes the silicon mobility and affects transistor performance. Furthermore, TSV, µbumps, and C4 produce a permanent stress in a zone around them. Modeling and characterizing these stresses is therefore important to examine the effect on device performance and reliability.
Figure 5 shows the TSV stress impact on transistors ION. This is fundamentally important to properly size the keep-out zone (KOZ) around the TSV, depending on the kind of circuitry in the region, whether it be analog (bigger) or digital (smaller).
Figure 5: TSV Stress Impact on Transistors ION
The impact of memory “cubes” on EDA is quite limited—mostly DFT, RC extraction and SPICE simulation. The impact of silicon interposers and memory on logic on EDA is more widespread, but still evolutionary. Aside from the above, place-and-route bears most of the impact, in particular floorplanning and routing, and multi-technology support for DRC/LVS and STA.
2D-IC tools can handle multiple “libraries”, but only one “process technology”. The key step here is the upgrade of STA, and DRC/LVS to support multiple technologies.
The “modeling” of TSV, µbumps, C4 bumps, and RDL is critical towards a homogeneous handling of 3D structures across the different views—electrical, logical, and physical—minimizing the manipulations, and guaranteeing the consistency.
The impact of true 3D stacks on EDA is more revolutionary. Pathfinding tools may be required to deal with the cost, performance, manufacturing, thermal, and test trade-offs, as well as helping to assess whether a 2D or one of the many flavors of 3D-IC integration is the most appropriate solution. The investment is huge, and cannot be blind. A clear path must be identified/agreed upon in advance, as the role of EDA is to automate, and not to invent the path.
Figure 6: Impact on the IC Implementation Flow
A Phased Approach, to Begin With
Based on the technology trends, their timeline and impact on EDA, a silicon interposer-based 2.5D-IC solution mitigates/removes most of the challenges, and is suitable for a wide number of applications (basically, all the applications where the form factor is not “the” problem). Last, but not least, the design flow is more readily available, as it requires only an evolution of existing EDA tools.
For the sake of clarity, a “silicon interposer-based 2.5D-IC” should be interpreted to mean a passive silicon interposer, single-sided, hosting two or more either homogeneous, or heterogeneous die, side-by-side; one or more die may actually be a homogeneous stack, such as a memory “cube”. Eventually, I/Os may be moved onto the silicon interposer; all die would shrink and become core-limited, thus leading to cost reduction. However, the silicon interposer would become active, which adds more complexity.
Figure 7: 2.5D-IC Physical Implementation
Synopsys is working with its leading semiconductor partners to develop, qualify and deploy a silicon interposer-based 2.5D-IC design flow. Figure 7 shows an example of 2.5D-IC, which is comprised of a 65nm silicon interposer, hosting logic, and memory die at different technology nodes.
Moving the global power and ground mesh onto the silicon interposer allows for either a simplified layers stack on the die (fewer masks mean simpler, cheaper process) or for increased area utilization (smaller die mean lower silicon real estate, thus leading to cost reduction). Partitioning the different subsystems onto different die allows for manufacturing each of them using the most appropriate process technology (again, fewer masks mean simpler, cheaper process technology on a per die basis and results in better yield).
Figure 8: Passive Silicon Interposer: Single-Sided, Side-by-Side, Some Homogeneous Stack
Leveraging Existing Tools
Existing design tools, methodologies, and flows can be upgraded in order to deal with 2.5D-IC integration. Most of the 2.5D-IC design flow (including standard cell placement, clock-tree synthesis, routing, optimization, etc.) is identical to an advanced 2D design flow. There is no evidence of showstoppers, and a limited number of new capabilities and features is necessary to make existing 2D EDA technology 2.5D-aware and capable.
Synopsys has developed a comprehensive and efficient silicon interposer-based 2.5D-IC design solution. Synopsys’ test tools have been upgraded to address 3D-IC designs, combining logic and memory test technologies based on existing standards for core-wrapping (IEEE 1500) and boundary scan test (IEEE 1149.1 and 1149.7). Synopsys is actively participating in the IEEE P1687 (a.k.a. IJTAG) standardization effort, which will be fundamentally important to “organize” the stack’s design-for-test (DFT) and design-for-debug (DFD) from a collection of potentially heterogeneous DFT/DFD on each tier. Synopsys is also a strong supporter of the IEEE P1838 standardization effort, aimed at providing test access to TSVs, necessary to detect defective interconnects between bare dies (i.e., bad TSVs), and to implement a redundancy/repair solution for TSVs.
Synopsys extraction tools have been upgraded to account for µbumps, TSVs, C4 bumps, and RDL both on the front and the back side of the wafers. Each tier is extracted separately, including all the 3D structures belonging to it. A hierarchical netlist instantiating all the tiers can be created, e.g., for electrical simulation purposes.
Synopsys HSPICE® and FastSPICE tools have been upgraded to understand the 3D structures. The models for the µbumps, TSVs, C4 bumps, and RDL are constantly being updated as a better and deeper understanding of the process technology-related aspects, as well as the reliability and accuracy requirements, is attained.
Synopsys’ physical verification tools have been upgraded to deal with 3D-IC as well. While using 2D tools for 3D designs is possible, it might not be very convenient. 3D structures and rules are easy enough to add to the DRC deck, but dealing with the LVS decks, and also manipulating the netlist, is much trickier.
Figure 9: Silicon Interposer (Detail) in IC Compiler
Figure 10: Silicon Interposer (Detail) Routed
Figure 9 shows a detail of the floorplan of the qualification vehicle shown in Figure 8, in IC Compiler. Figure 10 shows the same detail routed using IC Compiler Zroute technology. The beauty of Synopsys’ 2.5D-IC silicon interposer-based physical implementation solution is that it leverages existing tools. Consider a silicon-interposer as the top-level of a hierarchical design, and the various die as its hierarchical blocks.
- There are three key advantages to using IC Compiler Zroute technology for routing the silicon interposer:
- Capacity: Zroute is architected to deal with millions of nets. Zroute has no problem routing 10,000 nets, unlike tools designed for or derived from board-level implementation;
- Number of layers: today silicon interposers have up to 4 layers of metal, however, in the future the number of layers of metal may increase significantly. Zroute has no problem routing any number of layers;
- Automation: Zroute can automatically complete the routing of any number of nets and any number of layers.
Figure 11: µBump to TSV (Top Side) to C4 Bump (Back Side) Routing
Figure 12: µBump to TSV (Top Side) to C4 Bump (Back Side) RDL Routing
A 45°-capable RDL router is being developed to complement IC Compiler Zroute, which is a Manhattan router, whenever necessary for performance reasons, or due to “analog” requirements. Figure 11 shows a detail of a wide-wire (2-micron) route from the µbump (shown in red) to the TSV (shown in blue) to the C4 bump (shown in yellow). Figure 12 shows the RDL routing (shown in green) between the TSV and the C4 bump on the back side of the silicon interposer.
In addition, customers can use Galaxy Custom Designer® to pre-route analog nets. After initial floorplanning, and the power and ground (P&G) grid synthesis, Custom Designer can be invoked from within IC Compiler to do net shielding, differential pairs routing, or matched resistance routing. IC Compiler understands analog nets, which are not touched as Zroute completes the routing for the silicon interposer.
2.5D-IC can provide a smooth, cost-effective transition to 3D-IC design. A silicon interposer-based 2.5D-IC design flow is well within reach, and can be the “laboratory” for future 3D-IC design flow development. Further collaborative work is needed to minimize the technical and economical challenges. Blind investments, too often leading to dead ends, are not affordable. Future evolution and additional features depend on the findings of on-going work with leading semiconductor suppliers.
The following images are courtesy of their respective owners and used by permission. All additional images copyright 2012, Synopsys, Inc.
Figure 1: C.-G. Hwang, “New Paradigms in the Silicon Industry”, Samsung Electronics, IEDM Conference, 2006
Figure 2: J.T. Pawlowski, “Hybrid Memory Cubes (HMC)”, Micron Technology, Hot Chips Conference, 2011; and J. Rattner, “Ahead of the Curve, Straight to the Future”, Intel, Intel Developer Forum, 2011
Figure 3: XCell Journal, issue 74, Xilinx, 2011
Figure 4: Pascal Vivet, CEO-LETI and Vincent Guerin, ST-Ericsson, 3D Architectures for Semiconductor Integration and Packaging, 2011
Figure 5: V. Moroz1, P. Marchal2, E. Beyne2, et al., 1Synopsys, 2IMEC, “Reliability of 3D IC with Via-Middle TSV: Characterization and Modeling”, SEMATECH Design for Reliability Workshop, 2011
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About the Author
Dr. Michael Jackson
Michael Jackson is the VP of Physical Implementation R&D at Synopsys. He joined Synopsys in 2002 as part of the Avant! acquisition where he led the engineering efforts for physical design and simulation products. Michael received his Ph.D. in Electrical Engineering and Computer Sciences from the University of California at Berkeley.