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Issue 1, 2011
Expanding Synthesis-based Test for Higher QoR and Lower Cost
Robert Ruiz, Synopsys, explains how advanced test technology is enabling designers to achieve optimal quality of results (QoR) and eliminate time-consuming iterations between design and test, to keep pace with customers’ evolving requirements.
EDA businesses invest huge amounts of R&D resources into their test tools to reduce the time for chip testing. And rightly so – test time has a direct impact on chip economics. But out-and-out test time reduction isn’t the end of the story. Increasingly, design teams are looking for productivity benefits from their test activities throughout the entire design flow, from test integration through to yield analysis.
Integrating test with design significantly improves turnaround time in the test implementation stages of the design flow. In fact, our customers tell us that the difference between a synthesis-based approach to test and a bolt-on test solution can reduce test implementation from four weeks or more to just a couple of days.
Test Challenges Stay the Same
The fundamental challenges for test engineers have remained fairly constant: to enable the testing of as many parts as possible, to the highest quality, at the lowest cost. However, there are a number of design and technology trends that have made meeting these fundamental challenges more difficult.
Design complexity is growing, both in terms of the number of logic gates, increasing mixed-signal content, bigger memories and sophisticated power-saving architectures.
Test engineers have to make do with fewer dedicated test pins. This is because of increased focus on packaging costs, tighter form factors for portable applications, the prevalence of core-based design methodologies, and the need to satisfy multi-site testing techniques. The consequence of this is that test teams are looking for higher levels of test compression.
As design and test grow in complexity, the dependencies between the two domains are becoming far more difficult to manage in order to meet the throughput, quality, and cost constraints for test.
Test Impacts Design, Design Impacts Test
Adding test structures to the design to improve fault coverage can make it harder to reach design goals for timing, area, power and routing. At the same time, the complexities of the design itself can make it difficult to achieve the test goals. For example, design issues that test engineers must consider include the number of pins available for test, the amount and type of memory to be tested, and how to test structures across different power and voltage domains.
Converging on both design and test goals is becoming increasingly difficult when they are dealt with as separate tasks, which is what a “bolt-on” test flow has to do.
Bolt-on Test Undermines Productivity
Bolt-on test flows separate the key test implementation steps from RTL synthesis and design implementation.
Using bolt-on test flows means taking an iterative approach to test and design implementation. Using discrete test tools before synthesis – which lack knowledge of the final design, and after synthesis on the gate-level netlist – which requires additional synthesis processes to address the DFT logic impact on timing, are the main causes of iterations. Iterating between design and test often involves significant time, effort and cost.
Figure 1: Bolt-on test flow showing iterative steps
Some of the specific issues with bolt-on test flows include:
- Scan Compression Estimates
For designs that utilize scan compression logic, test engineers sometimes have to determine the compression architecture before the block itself is complete. In this case, there is a chance the architecture will be incorrect, which means updating the design and repeating all the implementation steps. If the steps aren’t repeated, the result will be a less-than-optimal compression architecture and likely decline in the quality of the test program generated by an automatic test pattern generation (ATPG) tool.
- Manual Stitching
The design team has to manually stitch any compression logic, created as separate RTL blocks before synthesis, to the final RTL. Any manual process is error-prone, and this becomes more challenging as compression techniques improve. Most errors introduced at this step are not caught until validation after synthesis. Unfortunately, scan chain validation does not predict the final ATPG result and therefore does not detect all compression architecture errors. In short, an error during compression IP stitching could cause iterations late in the design flow or decrease the test quality due to missing scan compression logic.
- Gate-level DFT
The archaic practice of replacing regular flip-flops with scan flip-flops at the gate-level, or “throwing the design over the wall”, is no longer sustainable. This process pays little or no regard to design constraints. Gate-oriented DFT tools “break” the design by not considering the connections across voltage/power domains, the timing impact from the dominant wire connection delays, or the area constraint for mobile and high-volume consumer designs.
- Scan Chain Congestion
Implementing high levels of test compression creates more routing congestion as a result of the many connections between the compression logic and the internal scan chains. Physical design tools can deal with the congestion, but doing so after the routing for the design has been optimized makes routing convergence difficult and time-consuming.
The best way to account for the effects of test logic on the design goals and design characteristics that affect the test goals is to combine design implementation and test implementation in RTL synthesis.
The alternative to using a bolt-on test solution is to integrate test implementation with design implementation. Synopsys synthesis-based test maximizes design and test teams’ productivity by embedding DFT in Design Compiler® RTL synthesis. The tools synthesize the test logic simultaneously with the functional logic, observing timing, power, area and floorplan constraints for test and functional logic.
Figure 2: Synthesis-based test flow maximizes design productivity
Synthesis-based test fully optimizes the test structures for test coverage and test data/time based on the design characteristics and constraints. Synthesis-based test delivers faster time to results because it minimizes the number of design iterations and accelerates convergence on both design and test goals. Some of the specific benefits include:
- Unified Test DRC
Hierarchical design involves block design and top-level chip assembly. Block designers can use synthesis-based test tools on modules before synthesis to verify they have met the DFT rules. The test DRC capability of Synopsys’ DFTMAX™ and TetraMAX® ATPG can provide feedback on the testability of the design during the pre-synthesis stage, which enables the designer to account for RTL testability early in the design process.
- Automatic Test DRC Fixes During Synthesis
Test DRC feedback enables designers to identify testability violations and fix them in the RTL. Designers achieve quick turn-around with a capability developed to automatically fix the testability violations within the synthesis environment while meeting timing constraints. Manual implementation of testability fixes at the gate level can break design constraints and invariably leads to additional synthesis iterations to preserve timing constraints.
- Minimizing DFT Area and Congestion
Integrating DFTMAX Compression with synthesis enables it to automatically minimize area for DFT. As an example, consider the case of a shift register. Such structures are inherently scanned and only require the first flip-flop to be replaced with a scan-flop and have the output of the structure fan-out to the next scan flip-flop. The alternative at the gate level is to replace every flip-flop with a scanned flip-flop. In the case of large graphic processor design, reducing the use of scan-flops saves up to 5% due to the heavy use of shift registers.
Another benefit of synthesis-based design is the ability to reduce congestion. DFTMAX Compression operates in conjunction with DC Graphical to proactively reduce congestion from the test compression logic and scan chain connections, reducing the amount of effort and time for physical design systems such as IC Compiler. DC Graphical has specific knowledge of the compression architecture generated by DFTMAX Compression and can apply congestion optimization techniques unique to the architecture.
- Automatic Handoff to ATPG
DFTMAX Compression minimizes the RTL design effort needed to generate test patterns by automatically creating the description of the scan chain operation or protocol file. The protocol file drives ATPG and must be in a valid, readable format. DFTMAX Compression creates the file using the IEEE 1450 standard (commonly known as STIL), which TetraMAX ATPG reads. The designer is only required to supply the netlist and library information to TetraMAX ATPG.
Testing complex chips requires dedicated test logic to be embedded throughout the entire design. Implementing test logic outside the synthesis flow adversely impacts design characteristics such as performance and power consumption, leading to iterations between synthesis and test that lengthen project schedules. In contrast, a synthesis-based approach implements test within RTL synthesis to minimize the impact on design power, timing and area, accelerating convergence on both design and test goals.
Broadening Test Technology
Synopsys is expanding and improving its synthesis-based test technology to further increase designer productivity, improve quality and lower cost across all areas of manufacturing test and yield analysis.
To accommodate the need for even lower test cost for pin-limited methodologies, as well as extremely large designs, Synopsys will provide higher compression utilizing synthesis-based technology to maximize designer productivity.
Embedded memories are a feature of most SoC design these days, so design teams need a robust test and repair solution. The DesignWare® STAR Memory System®, which is in widespread use today, delivers high-coverage, cost-effective self-test and repair of embedded memories. Synopsys plans tighter integration with synthesis-based test to ensure fast turnaround time and maximum scalability.
Use of high-speed SERDES interfaces, such as PCI Express and USB 3.0, is commonplace in SoC design. These interfaces can be hard to test. Synopsys’ test technology includes built-in self test (BIST) for high-speed IO, as well as verification IP to enable test integration.
New integration between TetraMAX ATPG and Yield Explorer yield analysis will enable designers to rapidly debug defective parts from a relatively small number of wafers. Yield Explorer can take information from TetraMAX ATPG to correlate defect location patterns. The design team can pin-point systematic issues using the tester fail information to decide whether to make any design changes in order to enhance the yield.
Synopsys’ synthesis-based test flow already eliminates time-consuming iterations between design and test. However, design teams are constantly looking for ways to shorten their schedules and improve throughput for all aspects of design and test. To address this need, Synopsys’ test roadmap is centered on broadening and strengthening its synthesis-based test technology to further increase the productivity gains, test quality and test cost savings designers achieve with Synopsys' solution.
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About the author
Robert Ruiz is the Senior Product Marketing Manager for the test automation products at Synopsys, Inc. Robert has held various marketing and technical positions for the test automation and functional verification products at Synopsys, Novas Software and Viewlogic Systems. His background includes over 17 years in advanced design-for-test methodologies as well as several years as an ASIC designer. Robert has a BSEE from Stanford University