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Issue 1, 2013
Going 3D by Evolution Rather Than Revolution: 2.5D, 3D, 5.5D-IC and Beyond
This article is based on the invited talks given by Steve Smith, senior director of marketing for 3D-IC strategy at Synopsys, at the “Design for 3D 2012” conference in Lausanne, Switzerland, and at the “3D Architectures for Semiconductor Integration and Packaging 2012” conference in Burlingame, California.
In 2004, a visionary keynote by STMicroelectronics’ Carlo Cognetti at the Napa KGD Packaging & Test Workshop entitled “Much More than Moore” proposed that “more than Moore” (i.e., the 3D-IC integration of complete, heterogeneous systems in the same package) is complementary to silicon-level integration, which is ruled by the well-known and established “more of Moore”, and suggested that the final result of combining “more than Moore” and “more of Moore” is surprisingly more advanced than what is allowed by the simple progression of the technology nodes.
At that time, the road to 3D-IC integration was unclear, R&D engineers at all levels of the supply chain were debating the different options, and 3D-IC was considered a technology of the future. We have made a great deal of progress, and today, 3D-IC integration has become the technology for the future rather than the technology of the future.
Why Now? Scoping the Challenges
The integrated circuit (IC) was invented by Fairchild and Intel co-founder Robert Noyce in 1959. Back then, it was only possible to integrate a handful of transistors, and engineers immediately started wondering how to integrate more. The first U.S. patents on 3D-IC and through-silicon via (TSV) technologies are more than 50 years old but have remained a solution without a problem until very recently, thanks to Moore’s law (the number of transistors per unit of area doubles from one technology node to the next, the cost per unit of area remains the same—about “one billion dollars an acre, that order of magnitude”, according to another Fairchild and Intel co-founder: Gordon Moore), and performance gets higher within the same, or even lower, power envelope. The solution now applies to a three-fold problem.
First, the cost per unit of area is no longer constant: a 100-square-millimeter die manufactured using a 20-nanometer foundry process technology featuring FinFET and double-patterning costs about 70 percent more than the same die manufactured using a 28-nanometer foundry process technology featuring a high-k metal gate (source: “The Economic Impact of Technology Choices”, IBS, 2012). The future will not be decided by what is possible but rather by what is affordable, and more than 2D-IC integration looks like an economically viable alternative to Moore’s law for most applications, especially those requiring more than just plain CMOS process technology: while digital blocks continue to shrink, analog hardly shrinks at all.
Second, as technology nodes advance, limitations in bandwidth begin to curtail the number of cores that we can effectively integrate on a single die and restrict the performance that we can reasonably achieve. As an example, in the Oracle T3, the 2.4Tbps bandwidth SerDes I/Os occupy about 60-square-millimeters of silicon real estate and consume about 30 watts, 15 percent of the die size, and 22 percent of the power consumption respectively (source: Jinuk L. Lin, et al., Oracle, “A 40 nm 16-Core 128-Thread SPARC SoC Processor”, IEEE Journal of Solid State Circuits, 46/1, 2011). A 20Tbps bandwidth, if implemented using state-of-the-art 28Gbps SerDes I/Os manufactured using a 28-nanometer foundry process, would require about 200-square-millimeters of silicon real estate, and would consume more than 200 watts (source: Ricki Dee Williams, et al., Oracle, “Server Memory Roadmap”, JEDEC Server Memory Forum 2011). The quest for higher bandwidth is possibly the strongest force driving us toward more than 2D-IC integration to improve performance while reducing power consumption.
Third, while Moore’s law is “alive and well” for transistors, the number of I/O pins per million of transistors keeps decreasing, thus hampering our ability to exploit a given technology node integration capacity to its full extent. The number of I/O pins per thousand of logic cells in the largest FPGA at a given technology node, which has decreased by 30X from 180 to 45/40 nanometers (source: Shankar Lakka, Xilinx, “Xilinx SSI Technology, Concept to Silicon Development Overview”, Hot Chips 2012); the 32/28 nanometer data point is not available, as Xilinx has moved from 2D- to 2.5D-IC integration at this technology node. I/O pins do not comply with Moore’s Law at all, and have become a precious resource. Silicon interposers—in both 2.5D- and 5.5D-IC configuration—can provide at least one order of magnitude more I/O resources than 2D-IC and 3D-IC.
Technology Trends and Timeline
Over the past few years, we have carefully looked at the technology and market landscape in close collaboration with our partners. We have concluded that an evolutionary transition from 2D- to 3D-IC integration is possible and is steadily progressing. Interestingly enough, 3D-IC was one of the EE Times hot technologies for 2012 (source: http://www.eetimes.com/General/PrintView/4231126), and 2.5D-IC is one of the EE Times hot technologies for 2013 (source: http://www.eetimes.com/General/PrintView/4403845).
Originally meant to be an interim solution, only a step on the ladder from 2D- to 3D-IC, evolutionary silicon interposers solve many of the 2D-IC “old” problems and don’t pose some of the revolutionary 3D-IC “new” problems. This is due to their much finer interconnect features (when compared to both package substrates and TSVs); silicon interposers will continue to play a fundamental role, at least until TSV pitch approaches the global wiring pitch (Mz, in the ITRS roadmap terminology), making the cost of horizontal and vertical connections more comparable, and TSV aspect ratio will get significantly better than today’s 10:1, making handling of thinned wafers easier.
Xilinx has successfully led the way with the world’s first homogeneous logic on silicon interposer in 2010 and the world’s first heterogeneous logic on silicon interposer earlier this year, both based on TSMC’s Chip on Wafer on Substrate (CoWoS) technology. The ecosystem is now in place and equipment manufacturers, silicon foundries, OSAT, and EDA companies have demonstrated the full technical feasibility of more than 2D-IC integration. Throughout 2013, we will see more announcements of 2.5D-IC products, a sign of growing confidence in the high potential of more than 2D-IC integration. 3D-IC is also progressing but not yet ready for takeoff. As an example, in spite of very promising results, 3D-IC integration of wide I/O memory and application processors for mobile applications has been postponed due to the significant improvements of classical DDR memory, which have made it possible to deliver the desired bandwidth using more traditional 2D-IC integration.
The Design Flow Is There
Synopsys’ R&D investments and recent announcements both stem from these conclusions: 1) leveraging our existing implementation and verification technologies, we can address the roadmap and the requirements of our partners as they emerge, incrementally, and 2) physical implementation, RC extraction, DRC/LVS, static timing analysis (STA), design-for-test (DFT) and SPICE simulation have been enhanced to support 2.5D-IC and 3D-IC design. We have not found any evidence of technical roadblocks and the enhanced EDA tools are available now.
For example, in physical implementation, we have complemented our best-in-class Manhattan router, which has proven extremely efficient in routing the silicon interposer interconnect with a new 45-degree-capable RDL router. Another example is in SPICE simulation, where we have expanded the capabilities of both modeling language and the simulation engine to support the co-simulation of different modules using different models and operating conditions.
Figure 1a: Silicon Interposer (Detail) Routed
Figure 1b: Die-to-Die (μBump to μBump) RDL Routing
Figure 2: Multi-Technology Electrical Simulation
Synopsys is collaborating with engineering teams that are ready to take advantage of the opportunities offered by 2.5D-IC and 3D-IC technologies as they emerge. For example, in order to help accelerate the design of heterogeneous 3D-IC systems using silicon interposer with TSV (a.k.a., through-silicon interposer, or TSI) technology, we have signed a collaboration agreement with A*STAR Institute of Microelectronics (IME) of Singapore and joined the TSI Consortium. IME and Synopsys will work together to demonstrate the design and manufacturing flow as well as optimize TSI technology for cost-effective and performance-driven applications.
Moving forward, there is much more to 3D-IC than just implementation or verification, and there are many opportunities to extend the traditional EDA solutions to support this emerging technology. For example, virtual and fast prototyping are ideal for highly heterogeneous systems such as 3D-IC; thermo-electro-mechanical simulation is also critical, and TCAD—while originally meant for process technology development—is an extremely powerful technology for modeling the thermo-electro-mechanical effects introduced by 3D structures.
Beyond the IC
3D-IC integration will enable even more complex forms of integration, complementing ICs with micro-electro-mechanical systems (MEMS), such as multi-axis accelerometers, compasses, gyroscopes, microphones, pressure sensors, etc. In smartphones and tablets, it is becoming common to see the application processor surrounded by MEMS on the same printed circuit board. In the future this can evolve to a 2.5D-IC integration, and finally to a full 3D-IC implementation in which the functionality is repartitioned among the various die for greater efficiency. Silicon photonics is a promising technology to enable continued performance scalability of “more of Moore” systems, as well as to spark the transition to a new generation of “more than Moore” systems, and is ideally suited for both 2.5D-IC and 3D-IC integration. There are many great opportunities to extend the breadth of EDA solutions to accelerate these innovative technologies.
Contrary to some claims, the sky is not falling. If there is one outstanding challenge critical to making 3D-IC ready for prime-time, it is collaboration, the willingness of all involved parties to work together, sometimes sharing the burden of debugging and improving the existing features, testing them again and again, accepting temporary workarounds while waiting for a new feature to become available, always acknowledging that technology is only seldom perfect since its inception, and knowing that this joint effort will reap rewards.
About the Author
Steve Smith is currently responsible for Synopsys' 3D-IC strategy and marketing. He has been with Synopsys for 15 years, having served in various functional verification and design implementation marketing roles. He has worked in the electronic design automation and computer industries for more than 30 years in a variety of senior positions, including marketing, applications engineering, and software development. Prior to Synopsys, Steve worked at Viewlogic, CrossCheck, Teradyne, Unisys, and ICL. Steve holds a bachelor's degree in statistics and numerical analysis from Lancaster University, England.