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Issue 1, 2012
Combining Tools and Technology for 20nm Gigascale ICs
Synopsys and Samsung explain how they are aligning their respective technology roadmaps to address the emerging
challenges for next-generation 20nm process nodes.
The industry continues to invest in next-generation process technologies because the benefits are so compelling. According to Samsung, the move to future 20nm processes from today’s 28nm state-of-the-art technologies promises 35% performance gains, 55% improved density and 50% active power reduction. Design teams are hungry for technology that will enable them to continue to deliver high-performance designs with low power.
While the benefits of technology migration are significant, so too are the manufacturing and design challenges that we have to overcome. "We have been working closely with Synopsys to put in place infrastructure solutions for our 20nm technology. Synopsys' technology enabled us to quickly implement and validate our first 20nm test chip. The successful tapeout of this test chip marked a significant milestone towards design readiness for our 20nm process technology. Our partnership continues as we work together to overcome evolving 20nm challenges and to ensure future design success." Ana Hunter, vice president of Foundry North America at Samsung Semiconductor.
Collaborating to Enable Design
Overcoming design and manufacturing challenges at 20nm requires foundries and tool vendors to collaborate earlier in the design process and more closely than ever before. Design teams can only benefit from the most advanced technology process nodes if they also have access to the infrastructure – tools, intellectual property and methodologies – at the same time that the silicon becomes available.
The 20nm process technology challenges are different from 32/28nm processes, as 20nm technology is dominated by sub-90nm pitch lithography patterning issues. New litho-dominated design rules are required to extend 193nm immersion lithography to the 20nm process. Additionally at 20nm, the current single patterning lithography approach supporting IC manufacturing reaches a theoretical limit in the minimum resolution for silicon structures. To go beyond this limit, foundries like Samsung have chosen to employ Double Patterning Technology (DPT), which involves decomposing geometries on one layer into two masks instead of one mask, relieving interactions between adjacent shapes by increasing their spacing.
Samsung has chosen a gate-last scheme for optimal strain engineering, which is able to achieve optimal performance even for low-power technology. Other advanced technologies, such as middle-of-line local interconnects and aggressive lithography RET have also been employed and tuned to attain superior design scaling at the new node.
Samsung and Synopsys have a proven track record of collaborating to develop solutions for advanced process technologies. Most recently the companies successfully taped out the first test chip using Samsung’s high-k metal gate (HKMG) 20nm process technology. The design team used Synopsys’ Galaxy™ Implementation Platform, including Design Compiler® synthesis, IC Compiler place and route, In-Design physical verification with IC Validator, StarRC™ extraction and PrimeTime® signoff tools.
- Developing the test chip has helped us to refine several innovative solutions that address a raft of new 20nm technology challenges, including:
- Modeling new device structures
- Physical verification
- Advanced routing, including complex 20nm rules
- Design rule checking
We have focused on enhancing IC Compiler and IC Validator to enable fast routing throughput while delivering full compliance with thousands of complex design rules and manufacturable routing patterns. The next phase in 20nm development work continues to be focused on successful handling of Double Patterning in both IC Compiler and IC Validator which is key to our ongoing success.
Double Patterning Technology Key to Success
Process engineers have relied on optical lithography to create features on chips over the course of many generations of technology. Unfortunately, the dense logic patterns required by the latest processes are too small for even the most advanced optical lithography systems as the resolution of the photoresist patterns begins to blur at around 90nm pitch.
DPT is helping process engineers to extend the use of these advanced immersion optical lithography systems by printing wires of alternating tracks on separate masks, enabling them to achieve much higher feature densities (Figure 1).
Figure 1: Double Patterning Technology
While DPT helps to overcome a fundamental limitation of optical lithography, it creates other challenges that we need to overcome elsewhere in the design process. Adopting DPT mandates a new approach to several other key design implementation and physical verification tasks.
Mask decomposition is the process of decomposing geometries on one layer into two masks instead of one. The new masks are each sparse enough to address the lithography limitations. This process places an additional burden on physical design that now needs to generate layers that we can later decompose into two masks each, without undue impact on area, timing or turnaround time.
The layout generated during physical design must remain independent of the decomposition decision and must be universally decomposable. The question is how do we address those requirements during physical design?
There are a number of emerging solutions. Our preferred method enables place and route to use a combination of techniques to achieve the best balance between runtime, convergence and area. As double patterning has an impact throughout the design flow starting from placement to routing to extraction, we must provide a comprehensive DPT-Aware Place and Route solution. In addition to applying the more complex 20nm design rules, it is important to minimize the overhead of the Double Patterning related design rules. The possible rules are carefully evaluated and only the least invasive rules are applied. To make the DPT solution complete, we also combine a suite of other techniques very carefully with the automatically generated design rules to minimize the chance for any DPT violations in the final routing result. For example, at strategic points, we analyze and fix DPT violations locally during routing. Figure 2 below shows some DPT violations that the place and route tools would avoid.
Figure 2: DPT-Aware Placement and Routing
To reach convergence quickly, we can augment the tool with an In-Design flow to check for and correct any remaining violations with a signoff-quality decomposition check in the place and route environment.
Synopsys’ Solution at 20nm
Synopsys’ solution at 20nm incorporates IC Compiler Advanced Geometry together with IC Validator. This solution provides DPT-aware place and route, signoff-quality DPT analysis and automatic DPT repair. “Our collaborative work with Synopsys on double patterning technology is yielding excellent results. DPT is key to unlocking the performance, density and low-power potential of our 20nm silicon processes to the benefit of our mutual customers.” Dr. Kuang-Kuo Lin, Ph.D., Director, Foundry Design Enablement at Samsung Semiconductor.
IC Compiler Advanced Geometry (ICC AG) is a superset of IC Compiler. It includes all of the ICC features plus some additional 20nm functionality. This includes DPT-aware placement and routing, 20nm DRC and DPT rules and 20nm parasitic modeling.
The new configuration of IC Compiler includes innovative technology to formulate double patterning requirements as a generalized coloring problem, avoiding any potential conflicts and rendering a correct-by-construction solution that can be reliably decomposed during manufacturing. Central to this solution is IC Compiler's placement engine and the Zroute technology, which we have enhanced to be DPT-driven. In addition, IC Validator's In-Design physical verification has been enhanced for DPT compliance, enabling IC designers to verify before handoff to manufacturing that the target layers in the design are decomposable.
Synopsys provides the fastest path to DPT-compliant design using ICC AG, In-Design and IC Validator. Our solution comprises three pillars:
- The first pillar is DPT-aware place and route using IC Compiler AG, with the goal to provide the optimal solution without compromising area or runtime.
- The second pillar is the signoff-quality DPT analysis using IC Validator, which is available to use in the ICC AG environment through the In-Design flow.
- The third pillar is the automatic repair of any corner-case DPT violations identified by the signoff-quality checking in the place and route environment, eliminating any costly iterations between physical verification and implementation.
Solving the design and manufacturing challenges at 20nm requires close collaboration with our foundry partners. Our work with Samsung has delivered excellent results and provides the foundation for a strong technology roadmap that will enable our mutual customers to benefit from this advanced process node.
- More Information:
The following image is courtesy of the respective owner and used by permission. Figure 1: V. Wiaux et. al. Proc. of SPIE Vol. 6924.
All additional images copyright 2012, Synopsys, Inc.