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Issue 2, 2011
Synopsys and TSMC Go Virtual with 28nm Reference Flow

The new reference flow for TSMC’s 28-nanometer (nm) process technology introduces virtual prototyping, which allows project teams to develop software and tune the hardware architecture before silicon is available. Paul Lai, Synopsys, and Willy Chen, TSMC, explain how the latest enhancements help designers to shorten time-to-market and time-to-volume.

Extensive use of software is now critical in enabling product companies to get more from their hardware – for example, extending the use of chips across different applications, which increases production volumes and profit. That’s why system-level design has progressed beyond the chip – it’s imperative that semiconductor companies enable delivery of software with the chip itself.

Figure 1: System-on-chip (SoC) development is increasingly driven by software needs
Figure 1: System-on-chip (SoC) development is increasingly driven by software needs

Synopsys has worked with TSMC to extend TSMC Reference Flow 12.0 to provide a comprehensive methodology for earlier development and faster verification of software stacks and hardware platforms using Synopsys’ Virtual Prototyping and Synphony C Compiler high-level synthesis solutions. Designers can now optimize their high-level C/C++ code for performance and power using Synphony C Compiler, which has been optimized for TSMC’s advanced process technologies.

Other new features of the TSMC Reference Flow 12.0 include expanded manufacturing compliance capabilities and full support of TSMC’s latest 28-nm design rules and models within Synopsys’ Galaxy™ Implementation Platform. The new tool capabilities and system-level design integration enable designers to be more productive, get to market faster and reach volume manufacturing more quickly using TSMC’s 28-nm process technology.

Quick Start on Hardware and Software
The virtual prototype authoring tool, combined with Synopsys’ open transaction-level modeling (TLM 2.0) library, enables designers to quickly and automatically generate models and interconnects to create virtual prototypes. By integrating TSMC’s Power Performance Area model in the flow, hardware and software designers can now make TSMC technology node- and software-specific tradeoffs months earlier in the design flow.

Design teams can re-use their verification environments and use software-driven verification because of the links between the system-level flow SystemC™ TLM 2.0 and RTL models in Synopsys’ VCS®- based verification solution.

Reference Design for Reference Flow
The flow includes a virtual prototype that has been extended with a TSMC example H.264 video subsystem. In conjunction with the Linux SMP kernel and file system, also included, this example serves as a practical template for early hardware/software stack integration and demonstrates the full virtual prototyping debug and analysis capabilities. The reference flow also includes fully documented reference design examples for Synphony C Compiler.

Manufacturing Compliance
The Synopsys Galaxy Implementation Platform supports TSMC’s latest 28-nm design rules for manufacturing compliance from physical design through to signoff.

Design teams using Reference Flow 12.0 can take advantage of in-design physical verification. Design teams close to tapeout can use IC Compiler’s leakage optimization engine for final-stage leakage recovery. Reference Flow 12.0 also includes IC Validator’s pattern-matching technology, which enables fast detection and automated repair of manufacturing-limiting layout patterns.

Design teams can use Reference Flow 12.0 to make the most of TSMC’s most advanced process nodes through a convergent and predictable path, which helps them to develop a SoC from system-level concept to silicon.

TSMC Reference Flow 12.0 comprises a comprehensive set of Synopsys tools and IP for system-level, design implementation and verification, including:

System-Level Design
  • Virtual Prototyping and DesignWare® System-Level Library for SoC virtual prototyping and power/performance analysis
  • Synphony C Compiler high-level synthesis feeding into DesignCompiler® Ultra
DesignWare IP
  • DesignWare IP and Verification IP for the ARM AMBA® interconnect provides infrastructure and fabric components for AMBA 2.0 and AMBA 3 AXI3™
  • Automated assembly of the IP using coreAssembler tool
  • CustomSim™ and HSPICE® circuit simulation with TSMC 28-nm model support
  • VCS with MVSIM voltage-aware simulation
  • MVRC low power static checking
  • SoC ESL verification using VCS with UVM 1.0
Physical Implementation
  • IC Compiler place and route, including Zroute technology and dummy via insertion
  • IC Validator DRC/LVS In-Design physical verification and signoff
  • Custom Designer for DFM fixing using TSMC OA DFM fixing markers
RTL Synthesis and Test
  • DC Ultra™ and Design Compiler Graphical RTL synthesis including Topographical technology and congestion optimization
  • DesignWare Library datapath IP
  • Power Compiler™ power optimization and multi-voltage power management
  • Formality® equivalence checking
  • DFTMAX™ compression for test cost reduction
  • TetraMAX® automatic test pattern generation (ATPG)
Analysis and Signoff
  • PrimeTime® static timing analysis including advanced stage-based OCV
  • StarRC™ parasitic extraction with feature-scale VCMP, eDRAM tall contact, via-etch and trench contact modeling support
  • PrimeYield LCC for automatic lithography-hotspot and pattern-match detection and fixing, and TSMC unified LPC format support
  • Parasitic extraction, timing, IR-drop analysis
Rapid Yield Ramp
  • Yield Explorer for physical pattern-aware, design-centric volume diagnosis isolates and prioritizes the dominant systematic failures among the scan diagnostics results
  • Integration of systematic defect simulation data into yield analysis to quickly capture process marginality impacts on scan failures

Web links

About the authors

Willy Chen, TSMC
Mr. Willy Chen joined TSMC in 2000, and is currently responsible for the Design Methodology & Service Marketing Program at TSMC. The company’s award-winning Reference Flow is entering its 12th generation this year; interoperability initiatives including various interoperable techfiles and design kits are examples of results from this program.

He brings 17 years of experience in the semiconductor industry including IC design, flow development, design automation, technology management and marketing. Mr. Chen has a Masters degree in electrical and computer engineering from the University of California, Santa Barbara.

Paul Lai, Synopsys
Paul Lai is Group Manager Strategic Alliances, Synopsys and a veteran in the EDA industry with over 15 years experience. Prior to Synopsys, he held various management positions in applications, marketing, and strategic programs at Gateway Design Automation, Cadence, and Viewlogic. Currently, he manages the Synopsys strategic alliance program with key foundries. Paul earned B.S.E.E. and M.S.E.E degrees from Texas A&M University and an MBA degree from the University of California, Berkeley.

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