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Designing for Success: USB IP for FinFET Processes
By Morten Christiansen, Technical Marketing Manager, USB IP, Synopsys
SoC designers require continuous area reduction as well as improvements in performance and active and idle power. The continuous search for better transistors led to ultra-thin body, double-gate and Omega-gate transistors. FinFET is the latest development in the transition from discrete transistors via ICs, to VLSI, to ASICs, to SoCs, to complex SoCs. FinFETs enable higher performance, lower active and idle power, and smaller area, and are therefore the key to meeting the area and power requirements for process nodes below 28-nm.
For success when porting IP to FinFETs, IP suppliers must have a good understanding of the challenges associated with FinFETs, including the process complexities in modeling, parasitic extraction, power swings, fin width considerations and even lithography and manufacturing.
FinFET Challenges for IP Designers
FinFET transistors are a true 3D structure, unlike a planar FET. With this architecture, leakage or idle current can be reduced to almost zero. Linearity is improved and drain-source current is more closely related to the gate current.
Designing with FinFETs is more challenging than planar CMOS. Designers can not simply use existing 2D and 2.5D models for planar CMOS, because FinFET is a 3D structure that encounters more subdivided resistance and capacitance compared with a planar structure. The 3D structure requires a more complex model and more data manipulation than planar transistors making FinFET 3D device models far more complex. For example, even the effect of mechanical stress of the fins must be modeled and taken into account.
Furthermore, FinFET size is discrete. Transistor width (W), which is one of the main variables for tweaking transistor sizes, is no longer a continuum. Discrete fin sizing, multi-fin and compound transistors brings a new variable in design, without any easy workarounds, that designers have not previously encountered (Figure 1). Lastly, the rules for varying the channel length or body biasing are either much more restrictive or of limited benefit due to the intrinsic characteristics of FinFET technology.
Figure 1(a): Planar MOSFET Figure 1(b): FinFET Figure 1(c): Multiple fin FinFET
FinFET’s requirements for double-patterning limit designers with exacting layout rules. With FinFET gate delay variations across process, voltage and temperature (PVT) may become less pronounced; however, other process variations become first order effects. For example, variations caused by random dopant fluctuations, line edge roughness, and layout induced stress ultimately manifest as variations in device performance. Threshold voltage shifts and local currents can impact timing and power for digital circuits while severely varying performance for analog circuits. Discrepancies between the modeled circuit and the actual circuit extracted from the layout require an iterative process to close the gap. NTBI and PBTI aging effects are more pronounced and alter the behavior of the circuits.
The short story is that initial FinFET design is more challenging. The new process nodes used for FinFET are not as mature as the older planar CMOS processes. Design rules are still subject to change. Tool chains are new. Not all FinFETs are the same. Experience being the sum of all errors; design experience is almost zero. And failing in FinFET is expensive.
Even if FinFET is challenging, using FinFET enables SoC designs with smaller area, lower power and higher performance.
First Silicon Success for USB PHY in FinFET Process
High-speed PHY design is a combination of digital, analog, and RF design. Each new process node exhibits more variability in transistor performance and provides new challenges for high-speed PHYs. Using advanced design and verification methodologies is crucial to ensure that the PHYs work across all variations in process, voltage and temperature over the lifetime of the ASIC.
Synopsys works closely with foundries and lead customers to develop high-speed PHYs in FinFET. This ensures verified high-speed PHY IP is available at the same time as a new process node becomes available. As an example, the recently announced DesignWare USB femtoPHY is Synopsys fourth generation USB PHY, and each generation offered significantly smaller area (Figure 3) and lower power consumption. Contrary to popular belief, the area for analog circuits as used in high-speed PHYs does not reduce automatically with new process nodes. Many analog building blocks increase in size due to new design rules and constraints, and Synopsys achieved area and power reductions for each new PHY generation by designing new PHY architectures, innovative circuit solutions, and optimized designs based on a clear understanding of each new process node.
Figure 2: DesignWare USB PHY Generations
Synopsys USB femtoPHYs in FinFET have passed USB-IF compliance testing and are listed on the USB-IF integrators list. Passing compliance at room temperature and nominal voltage with a first-silicon testchip is laudable; however, it’s not sufficient for real-world designs. Therefore, Synopsys characterized the first FinFET testchips across voltage and temperature, including worst-case combinations as shown in the video below. Looking closely, you can see ice forming when testing at a bone-chilling -40C. At a blistering +125C, the ice and water evaporates.
||New DesignWare® USB 3.0 & 2.0 femtoPHY IP: FinFET Silicon Success
View the silicon test results of the new DesignWare USB femtoPHY family. DesignWare USB 3.0 and 2.0 femtoPHYs, available now on leading FinFET process technologies, reduce USB area by 50% compared to previous generations.
Sr. Product Marketing Manager, USB IP
First silicon success shows that Synopsys USB PHY designers understand FinFET technology. The transistor models and design tools are accurate. The USB PHY design is robust. With the success of the DesignWare USB 2.0 and 3.0 IP for FinFET processes, designers can architect FinFET SoCs with less risk, and SoC and product designers can concentrate on their core competencies.
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