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Using M-PCIe for Low-Power PCI Express Designs
By Richard Solomon, Sr. Technical Marketing Manager, PCI Express Controller IP
While PCI Express® has become the dominant I/O interconnect in PCs from ultrabooks to enterprise servers, it has largely failed to break into the tablet and smartphone space due to these applications' ultra-low power requirements. Great strides have been made in reducing PCI Express power with enhancements like half-swing drivers, Dynamic Power Allocation (DPA) controls, and new power-saving L1 sub-states. However, the challenges of driving PCIe’s high data rates across 16”-20” server channels have kept the power requirements of PCIe® PHYs well above what mobile devices can tolerate. For PCI Express to extend into the ultra-low power world of mobile devices, something drastic would have to be done.
Back in 2012, Synopsys and other companies founded a new PCI-SIG Working Group whose aim was to reduce PCIe power and bring its protocol, programming models, and wide spectrum of designs to the mobile space. Ultimately the group decided to replace the “legacy” PCI Express PHY and specify the MIPI Alliance’s M-PHY due to its proven power efficiency and range of speeds. In September 2012, the PCI-SIG and MIPI Alliance announced their collaboration with the ultimate goal of allowing device designers to easily move existing PCI Express designs to the new specification with little or no change to their existing PCI Express software infrastructure. Work proceeded quickly and by early 2013 the two groups announced the first version of the
M-PCIe™ Engineering Change Notification (ECN).
The M-PCIe ECN provides dramatic power savings over similar PCIe designs. Note that because M-PCIe is an ECN against the PCI Express 3.0 Base Specification, both documents are needed to completely specify an M-PCIe device. Figure 1 shows how implementing the M-PCIe ECN impacts a typical PCIe Root-Complex to Endpoint device path. A standard PCI Express path is represented on the left, and the new M-PCIe connections are shown on the right. The upper PCIe protocol layers– the Transaction Layer (TL) and Data Link Layer (DLL) – are unchanged in the M-PCIe devices. This ensures that the PCIe programming models are unchanged, and the application logic in each device can remain almost unchanged. The PCIe PHYs are replaced by M-PHYs, and the PHY interface changes from PIPE to RMMI. Only the Logical PHY Layer (LPL) is unique new logic for M-PCIe implementations.
Figure 1: Comparison of PCIe and M-PCIe architectures
PCIe and M-PCIe devices have different designs for their Link Training and Status State Machine (LTSSM). The M-PCIe ECN developers strove to maintain similarity between the two state machines, but the M-PCIe version of the LTSSM is ultimately a different design. While this is a significant change to every PCI Express device, the modification was necessary to control the
M-PHY's unique low-power states.
The PCI Express PHY is designed to drive across 16”-20” channels with as many as two sockets and two connectors (Figure 2). By contrast, the M-PHY is designed for use in much smaller, portable devices. For example, the mobile phone PCB shown in Figure 3 is less than 5” overall, with numerous chip-to-chip connections under an inch. Basic physics tells us that it will take much less power to drive a signal over a 1” run than over a 20” run. Thus the M-PHY, designed to drive much shorter trace lengths, can consume less power than a PCIe PHY at the same signaling rate.
Figure 2: PCI Express Server Channel 1
Figure 3: Mobile phone PCB (<5")
M-PHYs reduce power further due to the relationship between their operating mode and individual burst transfers. In an M-PHY design, the PHY is only at its maximum power while actually transmitting. Immediately upon completion of the burst transfer, the PHY drops to a much lower power “STALL” state and shortly thereafter into its lowest power “HIBERN8” state. Figure 4 shows these transitions and gives an idea of the order of magnitude power savings – STALL being perhaps half the power of the BURST mode, and HIBERN8 being less than half of STALL. By architecting for these rapid power state changes, M-PHY designers have minimized the amount of power consumed by active devices.
Figure 4: M-PHY power transitions
To further reduce power consumption, M-PCIe systems can implement asymmetric links, which allow for different numbers of transmitters and receivers on a link. The PCI Express Base Specification defines a PCI Express lane as having one transmitter and one receiver per device, ensuring that there are always an equal number of upstream and downstream lanes. Recognizing that some devices (e.g., broadband modems) may have asymmetric bandwidth needs, M-PCIe permits devices to implement whatever combination of transmitters and receivers needed. Consider the hypothetical device shown in Figure 5 which primarily receives data from PCI Express and moves it over another interface such as a broadband cellular link. Where PCI Express forces this device to have 4 transmitters and 4 receivers (shown on the left) to accommodate its need for 4 lanes worth of PCIe-to-cellular bandwidth, M-PCIe (shown on the right) permits the device to reduce the number of transmitters to only 2.
Figure 5: M-PCIe asymmetric links
While the M-PCIe specification allows devices to consume less power than they would with the PCIe PHY, PCI Express offers higher speeds than M-PCIe. M-PCIe uses three of the M-PHY “gears” for signaling rates. Each M-PHY gear can run at one of two different base frequency “rates” (known as Rate A and Rate B), but in very general terms one can consider M-PHY Gear M as being the same bandwidth as the corresponding Generation (M-1) of PCI Express signaling. So Gear 3 is roughly equivalent to PCI Express “Generation 2” (5.0 GT/s) signaling, Gear 2 roughly the same as PCIe “Generation 1” (2.5GT/s), and Gear 1 about half the bandwidth of PCIe “Generation 1.” While selecting an M-PHY for its power savings dramatically reduces the trace lengths, it requires a tradeoff in bandwidth.
The M-PCIe ECN provides dramatic power savings for PCI Express architecture designs. While the upper layers of the PCI Express protocol stack remain unchanged, there are some impacts to designers wishing to migrate designs from PCIe to
M-PCIe. As the Synopsys DesignWare® IP for M-PCIe IP is based on the silicon-proven PCI Express IP, choosing this IP can minimize SoC designers' risk and even implement both M-PCIe and PCIe in a single SoC. Visit synopsys.com/pcie for more information.
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