DesignWare Technical Bulletin 

A Simple Way to Use DesignWare Libraries in FPGA-Based Design Prototypes 

By Angela Sutton, staff product marketing manager, FPGA Synthesis, Synopsys

Today, we are seeing more FPGA-based prototyping systems being used to verify huge ASIC designs. These designs typically consist of 1000s of source files and implement the equivalent of a multi-million gate ASIC. Often the design verification engineer who is implementing and verifying this design in an FPGA is not the one who authored the RTL code. Furthermore, there are usually multiple engineering teams involved with the project, resulting in constant revisions and frequent handing off of the RTL. With all these complexities, it is critical for hardware, software and verification teams to be able to maintain a single set of “Golden” source files that enables them to quickly and efficiently validate the RTL modifications made by the multiple teams and avoid potential pilot errors. Figure 1 shows the typical design hand-off process from the ASIC hardware team to the verification and software development teams.

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Figure 1: Typical design hand-off process from ASIC hardware team to the verification and software teams

Implementing DesignWare Libraries in an FPGA Prototype
When prototyping an ASIC or portion of an ASIC within an FPGA, designers must determine how to handle a design’s RTL source files when they include instantiated DesignWare® Library Building Block IP or DesignWare Library Microcontrollers and AMBA. Two questions must be answered: First, Can the designer be confident that the FPGA synthesis tool will know how to implement all of these building blocks? Second, will DesignWare Component support be in sync with what is being implemented by the ASIC hardware team using their ASIC tools? With Synopsys FPGA implementation tools and DesignWare Library IP, the answer is “Yes.”

With the Synopsys flow, you can use the same complete and synchronized set of DesignWare Library components in your ASIC and FPGA synthesis and simulation flows. We will describe how to run the FPGA prototyping flow later in this article, but first, let’s take a look at the IP itself.

DesignWare Libraries: Building Blocks, Microcontrollers and AMBA
Figure 2 summarizes the IP available in Synopsys’ DesignWare Library. The DesignWare Libraries can be divided into two categories - DesignWare Building Blocks and DesignWare Microcontrollers with AMBA. All DesignWare IP can be synthesized in your ASIC and FPGA-based prototype, allowing you to maintain a single source of RTL for your design.

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Figure 2: Both an ASIC and an FPGA prototype can include DesignWare Library IP that is instantiated directly in RTL


The Building Block IP and the microcontrollers with AMBA each have, a slightly different design flow:

DesignWare Building Block IP includes memory, database, data integrity, DSP and test functions that you can instantiate directly in your RTL. The same set of DesignWare components are supported for both ASIC and FPGA designs, allowing you to use the same RTL source for your ASIC and your FPGA-based prototype. More details can be found here.

Figure 3 shows an example of inferring a floating point multiply-and-add component within Verilog RTL. VHDL support is also provided. This RTL code example can be used directly in both an FPGA prototype design and an ASIC design.

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Figure 3: An RTL example showing how to infer DesignWare component DW_fp_mac

DesignWare Microcontrollers with AMBA peripherals are configured using the Synopsys coreConsultant software and then read by your Synopsys FPGA or ASIC synthesis tools. More details about the IP can be found here. Figure 4 shows that, as in the ASIC flow, IP in the FPGA flow is configured using coreConsultant and encrypted prior to FPGA synthesis.

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Figure 4: FPGA-based prototypes of ASIC designs can include DesignWare Microcontrollers and AMBA peripherals

Using DesignWare Libraries in an FPGA Flow
Using DesignWare Library components in Synopsys’ FPGA-based prototype is simple. If you are using DesignWare Building Block IP in your FPGA flow, first ensure that the libraries are accessible to Synopsys’ Synplify Premier and Certify FPGA synthesis tools. On the other hand, the DesignWare Microcontrollers and AMBA peripherals can be configured using the coreConsultant tool and should then be included in your Synplify® Premier/Certify® design project prior to synthesis. These flows are depicted in Figure 5.

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Figure 5: Synplify Premier and Certify FPGA synthesis read DesignWare Building Block instantiations and DesignWare Microcontroller/AMBA IP directly, allowing you to use the same RTL source for your ASIC and your FPGA-based prototype

Accessing DesignWare Building Block from Synplify Premier and Certify
If you are using DesignWare Building Block IP, let Synplify Premier and Certify FPGA synthesis tools know where the DesignWare Library is located.
  1. On the machine on which you are running Synplify Premier/Certify, configure the DesignWare license server by setting the variable
    LM_LICENSE_FILE=port@server
  2. Include the following in your Synplify Premier/Certify TCL file to specify the DC root installpath and then enable the DesignWare Building Block IP to be accessed. These options can also be specified interactively via the Certify/Premier GUI from the Verilog/VHDL tab.
    set_option -dc_root "/home/<username>/tools/<DC release number> “ 
    set_option -dw_library {dw_foundation}

    If using minPower components use:
    set_option -dw_library {dw_foundation dw_minpower}

    This enables all DesignWare Building Block and minPower components to be used. It is also recommended that you set the following to ensure that the tool is accessing the DesignWare Building Blocks and not a legacy library:
    set_option -enable_DesignWare 0

Note that the DesignWare Building Blocks IP installation must occur on a Linux or Solaris machine, but this IP library can subsequently be accessed for FPGA synthesis by Synplify Premier and Certify software on a PC running Windows or Linux. In many cases, you may simply want to point to the exact same DesignWare IP installation that the ASIC hardware design team with whom you are collaborating is using.

Using Complex DesignWare Cores in an FPGA Prototype
Most of the same digital DesignWare IP cores including PCI E, USB 3.0, MIPI, DDR, SATA and HDMI, that you are using in your ASIC can be prototyped in an FPGA by using the coreConsultant software to configure the core and generate your normal ASIC RTL. Include this core’s RTL in your FPGA synthesis project, ready for synthesis and implementation in the prototype.

When prototyping an ASIC, the design verification and software development team will typically need to perform the following tasks:
  1. Controller + PHY interoperability validation
  2. System compliance testing
  3. Subsystem integration
  4. Early firmware and software development

The risk associated with the first two tasks of compliance testing and controller/PHY interoperability is significantly reduced when using the DesignWare cores with Synopsys’ HAPS® prototyping motherboards, since these tasks have already been performed before by Synopsys.

An example of the use of a DesignWare USB 3.0 core with the HAPS FPGA-based Prototyping Solution is shown in Figure 6.

fig6
Figure 6: Synopsys USB 3.0 application development, software development, demonstration platform that interoperates with Synopsys HAPS Prototyping Boards

HAPS prototyping motherboards are available in a variety of configurations ranging from 1 to 4 high-end Xilinx Virtex®-5 or Virtex-6 FPGAs. Additionally, boards are additive, meaning they can be tessellated to add more capacity. High-speed HAPS I/O daughter cards allow high-speed interface standards including PCIe Gen 2, SATA 6Gbps, and Gigabit Ethernet to be used in conjunction with the HAPS-60 or HAPS-50 based ASIC prototype. HAPS interface adapters are available, allowing you to build, for example, ARM-based prototypes by enabling the HAPS motherboard to talk to an external ARM daughter card supplied by ARM. HAPS memory daughter cards allow you to add additional memory capacity for prototyping or debug purposes to your prototype design. More information about the HAPS FPGA-based Prototyping Solution is available here.

Conclusion
With the cost of a mistake in a tape out of an ASIC design being so high, and with system design cycles being so long, designers are turning to FPGA-based prototyping to perform at-speed or close to at-speed validation of their ASIC design prior to tape out. These prototypes also form a software development platform, enabling the system software team to test and integrate applications that will eventually run on the ASIC design.

Today, many ASIC hardware designs reference DesignWare Library IP in their RTL to gain higher ASIC QoR and greater productivity through the abstraction and ASIC optimizations available for these components. The ability to synthesize FPGA-based prototypes from the same RTL design source that references these DesignWare components is key to allowing both the ASIC hardware team and the FPGA verification team to operate from the same synchronized set of RTL source files and IP. This is particularly desirable because FPGA-based verification typically proceeds based on snapshots of the design, where updates to the source are expected to occur frequently as the design evolves. These very updates must then be reflected quickly in a new revision of the prototype.

Certify and Synplify Premier software can read and synthesize FPGA prototypes from ASIC RTL that references DesignWare Library IP. This enables a single source file to be maintained when the design is being validated or prototyped in an FPGA. For users of complex DesignWare digital cores, HAPS prototyping systems can help eliminate Controller + PHY interoperability validation and system compliance testing steps, reducing project risk and saving you significant time.



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