If you are an IP designer, you are probably under increasing pressure to supply high-level models of your IP. Why? Well, because if you are a software developer, you are probably under increasing pressure to help differentiate your company's products by developing software that maximizes the benefits from the latest advancements in homogeneous and heterogeneous multicore systems. Which means you cannot delay software development until RTL models are available. And, as both semiconductor and electronic systems companies turn more and more to virtual prototyping for early software development, SystemC models are in high demand. This brings us back to you, the IP designer.
With an early start and high-level view into the complex hardware that IP designers create, software development tasks like OS porting and driver development are greatly eased and accelerated. However, the requirements for these types of models are tough to meet. Designers must enable high simulation speeds, full visibility and controllability while providing an accurate programmer's view of the actual IP. And, of course, all this needs to be available long before the RTL is ready.
The modeling effort is not small; however, it is not impossible to meet these requirements. Designers achieve higher ROI, not only from a software development perspective, but also from an IP block design view. There is a modeling methodology to write SystemC models while reducing the overall IP development time and effort.
Depending on the use case (e.g., software development, software performance analysis, architectural analysis or hardware verification), the model may need a different coding style and level of abstraction. For example, TLM-2.0 Loosely Timed (LT) is the preferred coding style for software development when using virtual prototypes. Combined with a coding style that promotes the separation of communication, behavior and timing, the SystemC Modeling Library (SCML) eases the creation of SystemC TLM-2.0 LT peripheral models. When developing a model of an IP block, it is important to create the model so that the communication, behavior and timing aspects are all independent elements, or in other words, so that the model is decomposed into orthogonal properties. Figure 1 below illustrates this coding style. Each element in the figure represents a modeling object or a piece of user code for a target component model. The benefit of SCML is that it adds modeling objects that provide an implementation of the key TLM-2.0 semantics and takes care of handling the speed and visibility requirements of the software development use case.
Figure 1: Target model coding style
As you can see here, using the SCML modeling objects not only eases the coding effort, it also enables visibility and controllability of the registers and memories and ensures fast simulation speed through support of the TLM-2.0 direct backdoor accesses to all storage elements in the system (memories and registers) and optimization of the quantum through the quantum keeper.
The best way to extend the benefits from the early creation of these SystemC IP models is to use them for software-ware driven verification of the targeted IP block. To verify the models, designers can build a simple virtual prototype running software to interact with and test the correct functionality of the IP model. Based on the embedded verification plan directed tests can be defined and run to achieve the right coverage and check if no assertions are being triggered. See the figure below.
Figure 2: TLM model verification
IP designers can then reuse this test suite to verify the RTL model of the IP. Not only does this reduce the development time of the RTL model as it can be verified against a golden reference model, the time to create the test suite is smaller as it can be done using a fast simulation infrastructure with powerful debug capabilities. And last but not least, the methodology improves overall IP model quality as the verification can be done in the context of a relevant system running a relevant set of software stacks, including booting an OS.
While the use cases for creating high-level IP models show clear benefits, the industry is still in a high demand, low supply situation. To that effect, the first industry-wide model portal has recently been launched: TLMCentral. Supported by leading IP vendors, service providers, EDA vendors and research institutes, this portal offers model developers, architects and software engineers across the design chain an infrastructure to collaborate on models, modeling methodologies and virtual prototype promotion. To find out more about available models or modeling methodology, this is a good place to start.