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Developing High-Performance 28-nm Data Converters with the SAR-Based Architecture
By Manuel Mota, Technical Marketing Manager, Synopsys
For designers using analog-to-digital converters (ADCs), the latest and greatest architectures can hold the key to reducing power, cutting area and increasing performance. The most recent advance is the introduction of Successive-Approximation Register (SAR)-based architectures for high speed, high resolution ADC implementations, due to their potential benefits in terms of power and area reduction and also their relative immunity to the “analog-unfriendliness” of advanced process nodes (28-nm) and beyond (16/14-nm).
The SAR architecture digitizes the input signal step-by-step by running a successive approximation algorithm and determining each bit in successive clock cycles until the complete conversion is finalized. This architecture reuses the same hardware for each step and requires a high clock rate to complete the conversion before the next sampling instant. For example, the SAR algorithm to determine 10-bits may take 10 or more clock cycles to complete, therefore the clock rate for this ADC needs to be 10 or more times higher than the rate at which samples are taken for conversion. Consequently, this architecture has traditionally been limited to low-speed and medium- to high-resolution applications.
Figure 1 shows the basic block diagram of a SAR ADC including a sample-and-hold (S&H), a comparator, a digital-to-analog converter (DAC) and a logic block (SAR). The input signal (Vin) is stored on the sample-and-hold and is successively compared to the output of the DAC, whose input codes are set by a logic block depending on the result of the previous comparisons.
Figure 1: Basic block diagram of a SAR ADC
One interesting aspect of the SAR architecture is its inherent simplicity. Contrary to established architectures such as the pipeline, the SAR-based architecture does not rely on multiple stages (each containing large gain amplifiers) or on the detailed analog characteristics of the process to achieve performance. Rather it is a single-stage converter made of a comparator, which is inherently very compact and low power. Furthermore, it is mostly insensitive to the analog characteristics of the process.
However, due to the step-by-step “serial” processing of the sample, traditional implementations of this topology are inherently slow and typically make use of large capacitor arrays for moderate and high resolutions. These impact both area and power dissipation, making them inefficient for high-speed data conversion.
- On the other hand, this topology can be improved with a multitude of techniques that fully exploit the architecture’s potential for low power and increase the conversion speed. Example techniques are presented in the white paper Scaling ADC Architectures for Mobile & Multimedia SoCs at 28-nm & Beyond, including:
- Reducing clock speed requirements through internally self-timed operation
- Reducing capacitor array through introduction of additional floating capacitor arrays and calibration of the capacitor array
- Using alternative sampling strategies
- Using redundancy to simplify the conversion steps
- Interleaving channels to achieve highest speed
Given the high speed and processing power available with modern process nodes, at 28-nm and below, SAR ADCs applying these techniques are becoming very attractive even for high-speed applications where pipeline or parallel ADCs had been the norm.
SAR-Based ADCs in Wireless and Mobile Communications Applications
Designers of wireless transceivers require ADCs that can cover a range of sampling rates that can meet their market needs. Offering 80 MSPS, 160 MSPS and 320 MSPS, for example, support the requirements of wireless and mobile communications segments, where the ADC is one of the critical elements on a transceiver (Figure 2).
Figure 2: Block diagram of a communications transceiver, highlighting the analog front-end
Protocols such as WiFi 802.11ac and LTE-A which find usage in smart-phones and tablets and other power sensitive devices, make use of multi-antenna techniques like diversity and spatial multiplexing techniques to increase the data throughput or/and link range (Figure 3). These techniques require the conversion of multiple receive paths, each typically using an ADC instance. In this context, power and area optimization are critical. Other techniques such as Software Defined Radio (SDF) or Full Band Conversion (FBC) that require very high speed conversion also benefit from the efficient power/area parallelization.
Figure 3: Three-antenna wireless transceivers improve throughput and increase coverage
Synopsys DesignWare 28-nm SAR ADC IP
Synopsys understood the advantages that the SAR architecture can offer and developed proprietary techniques that resulted in a very efficient and robust solution. Synopsys’ new generation of high-speed ADCs for the 28-nm processes has migrated from the pipeline architecture to the SAR architecture, and was specifically engineered to take advantage of the high-speed of the process to minimize area and power consumption.
The baseline ADC resolution is 12-bit at a conversion rate of 80 MSPS. By implementing the techniques described above, an impressive 3X lower power dissipation was achieved compared to the previous generation Synopsys ADC, which had similar specifications and was based on the pipeline architecture. The SAR architecture offers a very compact structure with only a capacitor array, a comparator, and a logic block, resulting in an area reduction of up to 6X (see Figure 4).
Figure 4: Layout comparison of a 12-bit pipeline ADC (left) to a 12-bit SAR ADC (right) with similar performance requirements for an LTE application (single channel example)
- Achieving these large power and area reductions required a number of design techniques, some of which are made possible by the speed of the 28-nm processes:
- Internal building blocks are dynamic, resulting in a perfect scaling of power consumption with sampling frequency. This means that the power consumption of the ADC is internally optimized for any sampling rate that the application may require.
- The capacitor array is digitally calibrated to allow sizing by the noise constraint only, and not matching. This means that the total area of the sampling capacitor is minimized which reduces total area as well as simplifies the driving of the ADC. The calibration is run at start-up and does not need to be updated after supply or temperature variations because only stable and drift-free capacitor ratios need to be corrected. In the interleaved construction, the calibration corrects also for offset and gain mismatches.
- Internal operation is asynchronous, requiring only a clock rising edge to start the conversion. The internal processing of the sampled signal and the bit decisions are sequenced by the comparator ready signal and timing circuits. However, the ADC interfaces are clock synchronous, which simplifies the design of the circuitry that interfaces with it. This means that the ADC does not require a high frequency clock for its operation; the clock frequency should match the sampling rate.
- The operation is mostly insensitive to the clock duty cycle, and the ADC latency is only 5 clock cycles.
- Higher sampling rates, up to 320 MSPS, are achieved through interleaving of ADC baseline channels.
Synopsys understands that power and area reduction, as impressive as they are, are not the only criteria to select an ADC. In fact, just as important as these two items, other key criteria such as silicon validation and performance can be even more important. This is especially true in advanced process nodes, such as 28-nm, whose characteristics are far from ideal for analog designs.
Figure 5 shows the output of the 12-bit DesignWare® ADC implemented in a 28-nm process, performing at 80 MSPS and 320 MSPS. These spectra highlight the high performance possible when pursuing aggressive ADC area and power reductions in analog “unfriendly” nodes. They highlight the good performance and low distortion achieved by the ADC even while converting high frequency signals, which makes it very attractive for many broadband applications.
Figure 5: Power Spectral Density of 28-nm Synopsys 12-bit 80 MSPS (left) and 320 MSPS (right) ADC
Complete High-Speed Data Converter IP Portfolio
Synopsys DesignWare Analog IP includes the SAR-based High-Speed Data Converter IP in 28-nm processes. In addition, the IP portfolio includes 12-bit 320 MSPS, 160 MSPS and 80 MSPS Receive ADCs, 12-bit 600 MSPS Transmit DACs, 3 GHz Low Jitter Clock Generating PLLs, and 12-bit General Purpose 5 MSPS ADCs and 20 MSPS DACs. Additionally, Synopsys’ analog interface portfolio includes 10-bit 300 MSPS Video DACs and 96-dB Analog Audio Codecs.
Together, these IP products make up a complete portfolio of advanced analog IP solutions that enable SoC designers to take advantage of the benefits of process scaling in terms of area and power consumption, while integrating a complete analog interface for applications such as mobile communications (LTE and LTE-A) and wireless connectivity (WiFi 802.11ac), digital TV and satellite reception, mobile applications such as tablets and smartphones, as well as other multimedia analog interfaces in the digital home.
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