DesignWare Technical Bulletin 

This quarterly newsletter provides you with the latest information on DesignWare® IP, including in-depth technical articles, white papers, videos, upcoming webinars, product announcements and more. As the industry’s trusted IP provider, Synopsys is committed to providing you with the resources you need to help you lower integration risk and speed time-to-market.

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Featured Articles

• DDR4 Bank Groups in Embedded Applications - Learn how to take advantage of DDR4 SDRAM bank groups to achieve lower system power and higher overall bandwidth for your designs.

• Using Port Multipliers with a SATA Host for Higher Performing Storage – Understand how port multipliers provide a simple, cost-effective way to add additional storage to an existing SATA Host.

• Dolby MS11 Decoder for DesignWare ARC Audio Processors - Learn how Dolby's MS11 Multistream Decoder, optimized for the DesignWare ARC™ audio processors enable designers to implement a certified solution in multimedia SoC designs.

• What's New: Accelerate USB 3.0 IP Integration with USB University - Register today for a range of online introductory and advanced sessions.

Tips and Tricks: Prototyping Your USB 3.0 System in a HAPS Environment - Discover tips and tricks on how to address the hardware challenges of your prototype and get it up and running as quickly as possible.

In-Depth White Papers

• Advanced Verification IP Accelerates PCIe Integration Test
  This white paper gives a few pointers on what should be included in integration test and how to get it done efficiently.

On-Demand Webinars

• Designing with FinFETs
• Logic Libraries for High-Performance, Processor-Based, Energy-Efficient SoCs
• Accelerate PCIe Integration Testing with Synopsys’ Next-Generation Discovery Verification IP
• What, Where, Who? Integrating Audio Analog Functionality into SoCs (Mandarin)

Industry Articles

• Chip Design: Tomorrow's Semiconductor IP - Not Business as Usual
• New Electronics: Building an IP-XACT Design and Verification Environment with DesignWare IP
• ChipEstimate.com: Interfacing to sensors using Data Converter IP
• EELife: USB 3.0 Makes Itself Right at Home
• EETimes Memory DesignLine: Integrating Large-Capacity Memory in Advanced-Node SoCs
• Chip Design: Mitigating RFID/NFC Cost & Power Challenges

Videos

• MCCI and Synopsys Demonstrate USB 3.0 MTP
  MCCI demonstrates Media Transfer Protocol from Synopsys DesignWare USB 3.0 controller and PHY to a Windows PC or tablet.

• Why Can PHYs Have Fuzzy Eyes?
  Understand the key contributors for fuzziness, like inter-symbol interference, and how to reduce those contributors.

• CTLE or DFE?
  The performance of a SerDes can be judged on its receiver equalization type. Learn the differences between CTLE and DFE, and when each type is preferred.

• The DFE Tap Dance
  The PCIe 3.0 specification defines a simple CTLE and a single-tap DFE in its base spec, but most designs use adaptive CTLE and multi-tap DFE. See how and why different numbers of taps are needed.

• Equalization: Manual or Adaptive?
  Understand what adaptive equalization is and how it relates to CTLE or DFE equalization in a PHY.

• Minimize High-Speed PHY Risk for First Silicon Success
  With the months required to design, fabricate, and test high-speed PHYs, see how designers have confidence in their designs before they see the silicon results.

Customer Successes

• Fujitsu Semiconductor Selects DesignWare DigRFv4 M-PHY and DigRF 3G PHY IP for Customer’s 2G/3G/4G Baseband Design

News

• Fujitsu Semiconductor ASIC Design for 2G/3G/4G Baseband Processor in Volume Production with Synopsys 28-nm MIPI M-PHY
• GLOBALFOUNDRIES and Synopsys Partner to Provide Comprehensive Design Environment for Foundry's 14 nm-XM FinFET Offering
• Synopsys Announces Energy-Efficient 28-nm PCI Express 3.0 PHY with Support for 10GBASE-KR