Synopsys is introducing two new products that uniquely address the challenges of testing SoCs:
- DFTMAX™ Ultra addresses the most demanding test quality and test cost requirements with innovative synthesis-based technology that enables higher compression and faster test frequencies using fewer test pins—as few as one scan I/O pair for pin-limited test.
- The DesignWare® STAR Hierarchical System leverages IP- and core-level test to efficiently test the entire SoC, enabling engineering teams to cut their test integration time to a matter of days and bring their designs to market faster and with lower design and test costs.
As SoCs increase in size and complexity, higher compression levels are required to maintain low test costs and achieve higher test quality, even as fewer pins are being allocated for test. DFTMAX Ultra addresses these challenges with new technology that is built into Synopsys' Design Compiler RTL synthesis:
- Achieves 2-3X higher compression that significantly lowers test costs and enables higher defect coverage
- Allows high-speed shifting for further test time and cost reduction
- Scales down to one channel for pin-limited test
- Provides simplified, fast test implementation
Full Story: Synopsys Announces DFTMAX Ultra to Significantly Reduce Silicon Test Costs
Overview Video: Introducing DFTMAX Ultra
DesignWare STAR Hierarchical System
Increasing complexity also makes it essential to use analog/mixed-signal IP, digital logic cores, memory and interface IP. The DesignWare STAR Hierarchical System offers a hierarchical approach for rapidly implementing test for the entire SoC to meet cost, quality and schedule goals.
- Increases design and design-for-test (DFT) productivity with automatic test integration and validation of SoC, including analog/mixed-signal IP, digital logic blocks, memory and interface IP
- Optimizes test time and power consumption with dynamic parallel and serial test scheduling
- Re-use IP- and logic block-level test patterns at the SoC level, saving development time and effort
- Reduces test logic area and signal routing with streamlined hierarchical network based on IEEE test standards and managed by a modular server controller for all IP and logic blocks
- Reduces test development time by weeks with hierarchical access of IP and logic blocks
- Part of Synopsys' complete solution of test products, which includes DesignWare STAR Memory System, DFTMAX and TetraMAX
Full Story: Synopsys Announces DesignWare STAR Hierarchical System to Accelerate Silicon Testing of SoCs
Overview Video: Introducing the DesignWare STAR Hierarchical System
Introducing DFTMAX Ultra
Introducing DFTMAX Ultra, a new synthesis-based test product that delivers higher compression to reduce silicon test costs.
Antun Domic, General Manager, Implementation Group, Synopsys