Seminar Series Europe 

2014 Technology Update Seminars 

These deeply technical events are designed to ensure that you achieve the highest value and productivity from the latest releases of your Synopsys tool investment. Aimed at Engineers and Engineering Managers, these single day events will cover the updates to 2013.12 releases of the Galaxy implementation products for digital design. They will cover synthesis, test, equivalence checking, sign-off and low-power. There will also be advanced sessions to demonstrate new capabilities and to improve engineers debugging skills.

Tuesday, 11th February UK: Bristol, Hilton Hotel
Thursday, 13th February Dublin, Crown Plaza Blanchardstown
Tuesday, 25th February Cambridge, Trinity Centre
Thursday, 27th February Eindhoven, Synopsys

If required on the day you will be welcome to move between tracks. Each track will commence at 9.15am, with registration and refreshments from 9.00am. Visit: : for registration of any Synopsys event.

For more information please contact Rod Carroll

Synthesis and Test Track
Signoff and Low Power Track
9:15DC + PwrC 2013.12 Updates
During this session we will review important updates to Design Compiler and Power Compiler in the 2013.12 release. We will discuss advances in usability, correlation to layout and hierarchical flows along with improvements in the low power implementation flow
PT 2013.12 updates
In this session we will review highlights of the 2013.12 release of the PrimeTime tool suite, including performance updates, UPF support, and reporting and constraint checking enhancements.
10:00Hierarchical STA
During this session we will discuss approaches to hierarchical STA for ECO and signoff cycles, including the latest "Hyperscale" technology.
11:00RTL Exploration
RTL exploration is becoming a key part of the RTL design cycle. This session will outline the updates to DC Explorer which enables early synthesis and RTL Analysis with cross-probing in the 2013.12 release.
ECO capabilities
This session will discuss efficient ECO implementation including an introduction to the latest "physically aware" capabilities now available in the PrimeTime Advanced (ADV) package.
11:45DC Best Practice & Debug Review
This session will focus on practical methodologies for achieving the best quality of results using DC. It will review the common techniques used to improve both timing and area along with guidelines on effective DC debugging.
Parametric OCV is the latest variation modeling capability to be introduced to the Primetime product suite. We will compare and contrast POCV versus existing derate mechanisms and discuss the characterisation requirements of the flow.
13:30FM 2013.12 Updates
In this session we will review highlights of the 2013.12 release of the Formality including performance improvements and GUI enhancements.
Low Power UPF 13.12 update
During this session we will cover updates to IEEE1801 support with the galaxy flow. The update cover DC/ICC/FM. We will cover ease of use features as well as additional IEEE1801 construct support.
14:15Advanced Debug and ECO (FM Ultra)
FM Ultra is a new Formality add-on. In this session we will review how FM Ultra can assist in the rapid interactive implementation and verification of functional ECOs , and also explain how FM Ultra is very useful in other debugging contexts.
VSI-LP Introduction
During this session we will look at the next generation static checking tool for your IEEE1801 low power based designs. This tool has been architected from scratch to give enhanced TTR and reduced memory capacity. We will demonstrate how useful this tool is in writing correct UPF through to producing correct silicon.
15:15DFTMAX Ultra & DFTMAX Updates
In this session we will be introducing our latest low pin count compression technology, DFTMAX Ultra. We will then cover the main enhancements to DFTMAX which include further shared I/O CODEC flexibility and significant enhancements to OCC insertion. We will also cover new DFT support in DC Explorer.
Implementation Low Power Debug
During this session we will look at useful shell commands to implement and debug your IEEE1801 low power design intent with Design Compiler and ICC. We will also expand this to cover features with the GUI which are also designs to speed up the debugging process
15:45TetraMAX Updates
In this session we will be focusing on physical diagnosis improvements. We will cover how to use the new physical database server which provides minimal memory overhead for large designs, plus improved diagnosis accuracy. This is coupled with a new reporting feature to give detailed diagnosis information.
FM Low Power & FM debug
During this session we will cover an overview of low power effects on logical equivalence checking. We will also cover useful debugging techniques to ease debugging of low power designs.
16:45Q & A - CloseQ & A - Close