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SuperSpeed your SoC with USB 3.0
USB 3.0 operates at 5Gbps& delivers more than 10x the bandwidth of USB 2.0 for faster "sync-and-go" functionality between PCs and portable devices.

Virtualization of PCI Express I/O Devices
Learn how I/O Virtualization is addressed within PCI Express® and how to add it to an existing PCI Express interface.

Buying Time: Using Signal Integrity and Common Sense to Meet Timing Margins for High Speed Memory Interfaces
Signal integrity techniques to address margin eroders such as crosstalk, simultaneously switching outputs, impedance mismatch and inter-symbol interference.

Decoding the Real Low Power Benefits of DDR for Embedded Applications
Critical areas to consider for the lowest power DDR interface.

Avoiding the Landmines When Using a DDR Interface on your Next SoC
Common misconceptions of the DRAM market including the realistic commodity DRAM roadmap for DDR2, DDR3 & LPDDR products.

Achieving Optimal Performance and Low Power for SATA Device Designs
Learn how to utilize the DesignWare SATA Device IP core to implement the SATA interface into of mass storage devices.

Building a VMM-Based Constrained Random Environment for Bus Protocol Verification
Take advantage of the constrained random verification approach and work through the challenges and learn how to successfully implement the key features.

Building a Configurable Gigabit Ethernet Subsystem for ComplexSystem-0n-Chips
Accurately calculate the internal FIFO size for the target Ethernet application and see how an IP core can easily be configured for different applications.

Boost Memory Bandwidth in Your SoC Design
See how a single host IP core can be configured to support multiple SATA devices while maintaining high performance across all devices.

Guidelines for Mixed-Signal PHY IP Integration, Debug and Test
Learn more about the tasks of both the IP developer and integrator to ensure a fully functional SoC.

Connecting to DDR2: Mitigating High-Speed Challenges in SoC Designs
An overview of memory interface subsystem design approach and how a complete integrated solution can reduce risk and increase design quality.

High-Speed Interface Testing - Solving the Analog Test Problem with a Fast and Accurate Digital Solution
Built-in test solution for DesignWare PCIe, SATA and XAUI PHY IP, where at-speed analog test can be done on a pure digital tester running at 10 MHz.

The Complete USB 2.0 IP Solution: Understanding Today's Design Considerations and Managing Tomorrow's Challenges
Are you ready to integrate high-speed USB IP into your SoCs?

Rapid Verification of ARM11™ processor-based platforms, containing ARM PrimeCell® IP, using DesignWare® VIP
How do you design and verify a subsystem using the AMBA 3 AXI protocol with the least amount of effort and in the shortest amount of time?

Jumpstart AMBA™ 3 AXI™ Design Verification with xVC Enabled DesignWare Verification IP
The AMBA 3 AXI bus protocol is the newest and most capable on-chip fabric protocol introduced by ARM.

High Speed Serial Interconnects - What to Look for when Selecting an IP Vendor for PCI Express, SATA and XAUI
The challenges and solutions of high speed serial interconnects such as PCI Express, SATA and XAUI

Accelerating Verification of an AMBA 3 AXI Protocol-based SoC with DesignWare Verification IP
Key challenges faced in verifying AMBA 3 AXI bus protocol based design.

High Performance Datapath Design with DC Ultra
Best-in-class datapath technology from DC Ultra and DesignWare Library produces the best synthesis QoR.

Proven path to adding PCI Express to your designs: Faster. Easier. Better.
First in a series of webcasts from Synopsys covering PCI Express system-level design issues.

Solving the Design and Verification Challenges of AMBA-based SoCs
AMBA® enables designers to utilize IP-based methodologies at the subsystem level.