|Dialog Semiconductor and Synopsys Present: New DFTMAX Ultra for Squeezing Out More Test Compression with Fewer Pins|
The demand for pin-limited compression is being driven by tighter form factors, the design of multicore SoCs that require few pins per core for test access, and the adoption of multisite testing as a technique to reduce test application time and cost. In this webinar, we will highlight how Synopsys’ new DFTMAX Ultra is designed from the ground up to achieve high compression using fewer digital scan pins and a minimum of one pair of scan pins. Our guest speaker will then discuss how DFTMAX Ultra is being successfully deployed to lower the cost of testing mixed-signal designs at Dialog Semiconductor.
Richard Illman, Technical Staff Member, Dialog Semiconductor; Carl Holzwarth Corporate Applications Engineering Director, Synopsys; Chris Allsup, Marketing Manager, Synopsys
Apr 17, 2014
|TSMC & Synopsys Present: DFTMAX Compression, IEEE 1500-based Hierarchical Test & iJTAG|
As the complexity of systems-on-chip increases, so does the need to leverage standards-based methodologies to implement test in a hierarchical manner, across multiple cores.
Dr. Saman Adham, Senior Manager, TSMC; Robert Ruiz, Product Marketing Manager, Synopsys; Adam Cron, Principal Engineer, Synopsys
May 23, 2013
|Enabling 3D-IC Integration|
Hear how Xilinx is using SSI technology to deliver higher levels of integration and flexibility in FPGA products, and learn how Synopsys' silicon-proven tools are enabling 3D-IC integration.
Steve Smith, Senior Director, 3D-IC Strategy and Marketing, Synopsys; Shankar Lakka, Director of IC Design, Full-Chip FPGA Integration Group, Xilinx
Jul 18, 2012