Static and Formal
Verifying Clock Domain Crossings in Complex SoCs – Are You Sure You Caught All the Bugs?
Avoid missing a CDC bug that causes a silicon re-spin! The Synopsys VC CDC solution provides comprehensive CDC verification at RTL for any size design, up to and including SoC full-chip flat, enabling designers to find and debug CDC issues early in the design cycle. We’ll discuss why our solution will find bugs that purely hierarchical solutions will miss, and do so with far less designer impact than any other solution.
David Hsu, Director of Product Marketing, Static and Low Power Verification, Synopsys; Namit Gupta, Corporate Application Engineer (CAE), Verification, Synopsys; Kaushik De, Scientist at Synopsys, Design Verification, Synopsys
Jul 16, 2014