Static and Formal
Catching the Uncatchable Bugs with SpyGlass CDC: Comprehensive, Practical, and Powerful Analysis
In this webinar, we will discuss how the SpyGlass CDC solution enables comprehensive clock and reset domain crossing (CDC/RDC) verification for more than a billion gates, helping designers to avoid costly chip killer bugs, re-spins and achieve signoff quality verification.
Kiran Vittal, Director Product Marketing, Verification Group, Synopsys; Sean O’Donohue; Senior Corporate Application Engineer (CAE), Verification Group, Synopsys
Jan 26, 2016

Raising Design and Verification Productivity with SpyGlass Lint Advanced: The Next Generation of Lint
In this webinar, we will discuss how the newly introduced SpyGlass Lint Advanced solution identifies RTL issues at their source, pinpoints structural, coding and consistency problems in the RTL descriptions, and helps designers resolve issues quickly before design implementation.
Arbind Kumar Rohilla, Verification Group, Synopsys
Dec 08, 2015

Accelerating Coverage Closure by Complementing Simulation with Formal Verification
VC Formal’s unreachable coverage analysis capability can help verification teams save weeks of manual effort, and VC Formal’s SoC connectivity checking capability can help eliminate the very real likelihood of missed bugs using traditional methods of verifying the huge numbers of top-level and block-level connections. We will describe how VC Formal’s capabilities can be easily used for saving time and effort in these very common and important use cases. In this webinar, we will show two crucial areas where formal tools can quickly save time and effort in helping you meet your verification coverage goals.
David Hsu, Director of Product Marketing, Static and Low Power Verification, Synopsys; Anders Nordstrom, Corporate Application Engineer (CAE), Verification, Synopsys; Xiaolin Chen, Corporate Application Engineer (CAE), Verification, Synopsys
Oct 07, 2014

Verifying Clock Domain Crossings in Complex SoCs – Are You Sure You Caught All the Bugs?
Avoid missing a CDC bug that causes a silicon re-spin! The Synopsys VC CDC solution provides comprehensive CDC verification at RTL for any size design, up to and including SoC full-chip flat, enabling designers to find and debug CDC issues early in the design cycle. We’ll discuss why our solution will find bugs that purely hierarchical solutions will miss, and do so with far less designer impact than any other solution.
David Hsu, Director of Product Marketing, Static and Low Power Verification, Synopsys; Namit Gupta, Corporate Application Engineer (CAE), Verification, Synopsys; Kaushik De, Scientist at Synopsys, Design Verification, Synopsys
Jul 16, 2014