Static and Formal
Accelerating Coverage Closure by Complementing Simulation with Formal Verification
VC Formal’s unreachable coverage analysis capability can help verification teams save weeks of manual effort, and VC Formal’s SoC connectivity checking capability can help eliminate the very real likelihood of missed bugs using traditional methods of verifying the huge numbers of top-level and block-level connections. We will describe how VC Formal’s capabilities can be easily used for saving time and effort in these very common and important use cases. In this webinar, we will show two crucial areas where formal tools can quickly save time and effort in helping you meet your verification coverage goals.
David Hsu, Director of Product Marketing, Static and Low Power Verification, Synopsys; Anders Nordstrom, Corporate Application Engineer (CAE), Verification, Synopsys; Xiaolin Chen, Corporate Application Engineer (CAE), Verification, Synopsys
Oct 07, 2014

Verifying Clock Domain Crossings in Complex SoCs – Are You Sure You Caught All the Bugs?
Avoid missing a CDC bug that causes a silicon re-spin! The Synopsys VC CDC solution provides comprehensive CDC verification at RTL for any size design, up to and including SoC full-chip flat, enabling designers to find and debug CDC issues early in the design cycle. We’ll discuss why our solution will find bugs that purely hierarchical solutions will miss, and do so with far less designer impact than any other solution.
David Hsu, Director of Product Marketing, Static and Low Power Verification, Synopsys; Namit Gupta, Corporate Application Engineer (CAE), Verification, Synopsys; Kaushik De, Scientist at Synopsys, Design Verification, Synopsys
Jul 16, 2014