RTL Synthesis
Sunplus Technology Perspective: Achieving Superior Results and Shorter Schedules with Design Compiler (Traditional Chinese)
Maximizing IC performance and reducing area are key for Sunplus to deliver competitive and cost-effective multimedia products to market while meeting aggressive schedules. In this webinar, John Yeh CAD engineer will discuss how Sunplus uses the latest Design Compiler technologies to improve predictability, reduce schedules and achieve superior results. He will show how DC Explorer helps speed up the development of high quality RTL and constraints and allows early physical exploration. He will also discuss how Design Compiler Graphical enables Sunplus to achieve higher performance and tighter correlation to IC Compiler for faster design convergence.
John Yeh, CAD Engineer, Sunplus Technology
Jan 28, 2016

Sunplus Technology Perspective: Achieving Superior Results and Shorter Schedules with Design Compiler (Simplified Chinese)
Maximizing IC performance and reducing area are key for Sunplus to deliver competitive and cost-effective multimedia products to market while meeting aggressive schedules. In this webinar, John Yeh CAD engineer will discuss how Sunplus uses the latest Design Compiler technologies to improve predictability, reduce schedules and achieve superior results. He will show how DC Explorer helps speed up the development of high quality RTL and constraints and allows early physical exploration. He will also discuss how Design Compiler Graphical enables Sunplus to achieve higher performance and tighter correlation to IC Compiler for faster design convergence.
John Yeh, CAD engineer, Sunplus Technology
Jan 28, 2016

GUC ASIC Methodology: Higher Predictability and Superior Results with Design Compiler Graphical
Achieving higher performance, lower power and smaller die size in an efficient timeframe is key for GUC’s ASIC design services. In this webinar, Kazuyuki Irie, Department manager for GUC Japan discusses the challenges of a traditional ASIC design flow that required timing margin in synthesis for faster design closure; leading to less than optimal area and power results. He will discuss how GUC Japan recognized a Design Compiler Graphical based methodology that improves predictability, reduces schedule and achieves superior results for GUC Japan.
Kazuyuki Irie, Department Manager, GUC Japan
Oct 08, 2015

ARM Perspective: Area Reduction on ARM Mali Cost-Efficient GPUs
In this joint webinar, ARM describes methodologies, design choices and results achieved by an area-centric reference implementation of the ARM Mali GPU using Design Compiler Graphical and IC Compiler.
Pierre-Alexandre Bou-Ach, Physical Design Lead, ARM; Priti Vijayvargiya, Director of RTL Synthesis Product Marketing, Synopsys
Apr 23, 2015

Accelerate your design closure with DC Ultra
Join this webinar to hear directly from senior product team members on how you can achieve superior results faster utilizing sophisticated optimizations of DC Ultra.
Sandra Ma, Synopsys; Janet Olson, Synopsys
Apr 21, 2009



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