Professional Services
DDR Hardening - A Repeatable Process to Predictive Closure
Learn from Synopsys Professional Services experts how to accelerate hardening of DDR interface IP in context of SoC design and performance requirements.
Vikas Sethi, Manager, Professional Services, Synopsys; Karan Jain, Design Consultant, Professional Services, Synopsys
Jul 28, 2015

Moore's Cores - Best Practices to Optimize Processor Cores for Performance, Power and Area Targets Specific to Your SoC
As silicon capacity continues to grow following Moore's law, so has the growth in computational power. This, along with the complexities of today's designs, has led to the need for multi-processor core SoC's to achieve design goals. Managing the complexity of designs that include CPUs, GPUs, and DSPs in a single chip can be quite challenging. Based upon years of Synopsys' consulting experience implementing hundreds of these SoC's, this webinar will outline design best practices and pitfalls to avoid, to enable you to achieve the right balance of high performance, low power and smaller area.
Jonathan Young, Director, Design Consulting, Synopsys
May 13, 2014