Professional Services
Moore's Cores - Best Practices to Optimize Processor Cores for Performance, Power and Area Targets Specific to Your SoC (in Mandarin)
As silicon capacity continues to grow following Moore's law, so has the growth in computational power. This, along with the complexities of today's designs, has led to the need for multi-processor core SoC's to achieve design goals. Managing the complexity of designs that include CPUs, GPUs, and DSPs in a single chip can be quite challenging. Based upon years of Synopsys' consulting experience implementing hundreds of these SoC's, this webinar will outline design best practices and pitfalls to avoid, to enable you to achieve the right balance of high performance, low power and smaller area.
HuaMin Hou, Senior Design Consultant, Synopsys
Aug 27, 2014

Moore's Cores - Best Practices to Optimize Processor Cores for Performance, Power and Area Targets Specific to Your SoC
As silicon capacity continues to grow following Moore's law, so has the growth in computational power. This, along with the complexities of today's designs, has led to the need for multi-processor core SoC's to achieve design goals. Managing the complexity of designs that include CPUs, GPUs, and DSPs in a single chip can be quite challenging. Based upon years of Synopsys' consulting experience implementing hundreds of these SoC's, this webinar will outline design best practices and pitfalls to avoid, to enable you to achieve the right balance of high performance, low power and smaller area.
Jonathan Young, Director, Design Consulting, Synopsys
May 13, 2014

Using FPGA-based Prototyping to Validate IP Integration Without Breaking a Sweat
Learn how to test DesignWare USB 3.0 interface IP and implement it on a HAPS FPGA-based Prototyping System. Review best practices on how to utilize Synopsys' Identify HW/SW tools to test the interface in the context of the larger chip design.
John Kuhns, Synopsys Professional Services, Senior Design Consultant
Jul 17, 2013