Physical Implementation
STMicroelectronics Deploys PrimeTime ECO Noise Fixing to Reduce Noise Violations by More Than 95%
STMicroelectronics will outline how PrimeTime ECO noise fixing fits with their PrimeTime and IC Compiler signoff flow, and share some results from real designs showing 95%+ noise fixing rates.
Sebastien Marchal, Principal Engineer, STMicroelectronics; Stephan Mahnke, Staff Corporate Applications Engineer, Synopsys
Jul 29, 2015

STMicroelectronics Deploys PrimeTime ECO Noise Fixing to Reduce Noise Violations by More Than 95% - Traditional Chinese
STMicroelectronics will outline how PrimeTime ECO noise fixing fits with their PrimeTime and IC Compiler signoff flow, and share some results from real designs showing 95%+ noise fixing rates.
James Chuang, Senior Technical Marketing Manager, Synopsys
Jul 29, 2015

STMicroelectronics Deploys PrimeTime ECO Noise Fixing to Reduce Noise Violations by More Than 95% - Simplified Chinese
STMicroelectronics will outline how PrimeTime ECO noise fixing fits with their PrimeTime and IC Compiler signoff flow, and share some results from real designs showing 95%+ noise fixing rates.
James Chuang, Senior Technical Marketing Manager, Synopsys
Jul 29, 2015

Advanced Mixed-Signal Design and Verification of Smartcar ICs
In this webinar, Micronas and Synopsys discuss the breadth of automotive IC applications, challenges in design implementation and verification and the solutions that stemmed from their collaboration.
Mario Anton, Micronas; Gernot Koch, Micronas; Marco Casale-Rossi, Synopsys
Jul 31, 2014

Imagination and Synopsys: Reduce Dynamic Power and Area up to 50% on a GHz+ MIPS Core Implementation
In this webinar, Imagination Technologies will share how their selection of standard cell architecture and use of several dynamic power techniques available in Design Compiler and IC Compiler helped them achieve optimal power and area savings for their MIPS family of CPU cores.
Maya Mohan, Hardware Design Engineer, Imagination Technologies and Jeffrey Lee, CAE Manager, Power Compiler, Synopsys
Jul 10, 2014

Accelerating Time to a Quality Floorplan: Cisco Systems and Synopsys Share Their Insights
Learn how IC Compiler’s new Data Flow Analysis (DFA) technology enables designers to accelerate time to a quality floorplan. Cisco Systems shares their experiences deploying this technology on a 100+ million gate ASIC to reduce floorplanning iterations with ASIC vendors and quickly identify and validate macro placement for the best quality of results.
Krishna Kumar Gundavarapu, Technical Leader, Cisco; Steve Kister, Technical Marketing Manager, Synopsys
Apr 23, 2014