Best of SNUG
Best of SNUG: New In-Design Features (IC Compiler, IC Validator, PrimeRail)
In-Design reliability analysis and physical verification save time by avoiding useless translations of data back and forth and also allow users to catch and fix problems on-the-go, preventing costly iterations between implementation and signoff.
Salvatore D'Argenio, STMicroelectronics, France
Jun 10, 2010

Best of SNUG: Galaxy Constraint Analyzer: Constraint Debugging Made Easy
In today’s designs, it is not unusual to have hundreds of clocks, power management, multiple modes, in-house or third-party IP with their own set of timing constraints that need to be integrated at the top level. This increased complexity together with tighter schedules makes finalizing the design timing constraints extremely challenging.
Emmanuel Pluchart, Synopsys, France
Jun 10, 2010

Best of SNUG: Clock Tree Implementation Techniques—A Comparative Analysis
This paper demonstrates two techniques of clock tree implementation with comparative analysis data. The first is a traditional cluster-based clock tree common in ASIC flows (CTS), the other is a unique technique used in various high-frequency designs based on non-uniform fishbone mesh.
Ina Shtarkberg, Intel Corporation
May 06, 2010

Best of SNUG: Simulation Acceleration using Multicore Systems
In this paper we show how to take advantage of multicore systems to accelerate simulation performance. First, we introduce an algorithm for automatically partitioning the design for multicore simulation. Second, we present an approach to use the GPU to further increase simulation acceleration (around 100X faster).
Itai Yarom, Intel Corporation
May 06, 2010

Best of SNUG: Scan Compression with Limited Pin Access
This presentation covers how the latest pin-limited testing enhancements have been deployed successfully on Wolfson’s latest devices.
Chris Dodd, Wolfson Microelectronics plc, UK
May 06, 2010

Best of SNUG: Scan Compression without 'Scan Compression'
DFTMAX compression can achieve over 100X compression. However, small compression factors can be achieved using ”multi-mode” scan architectures. For small- and medium-size mixed-signal designs these provide a low-cost alternative to full compression.
Richard Illman, Dialog Semiconductor, UK
May 06, 2010

Best of SNUG: Reducing the Cost of Pin-Limited Test using DFTMAX Compression
Designers are increasingly adopting DFT methodologies that limit the number of pins allocated for manufacturing test. In this tutorial, we examine what is driving this trend and how you can use new capabilities in DFTMAX to reduce the cost of pin-limited test for your designs.
David Johnson, Synopsys, UK
May 06, 2010

Best of SNUG: Effective Post-Layout Verification of AMS Designs at 28nm
Strategies and methods for correct Extracted View Sets generated with StarRC and results from a real design implemented at 28nm show how post-layout verification can be sped up, substantially improving the turnaround time of the AMS design flow.
Hendrik Mau, GLOBALFOUNDRIES, Germany
Apr 28, 2010

Best of SNUG: IC Compiler Feasiblity, Planning and Implementation
This tutorial addresses feasibility during the pre-route stages of the design flow and introduces an automated way to identify and analyze problems that impact timing, routability and congestion.
Rainer Hadwiger, Synopsys, Germany
Apr 28, 2010

Best of SNUG: Experiences with IC Compiler Black Box flow
This paper describes using the black-box flow in IC Compiler for early floorplanning analysis and timing checks in a 65nm ASIC with large busses. This approach saves development time and, for the first time, supports a real RTL-backend co-design.
Herbert Preuthen, LSI, Germany
Apr 28, 2010



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