Architecture Design
Optimizing Quality-of-Service (QoS) with Interconnect and Memory Subsystem Analysis
Sponsored by Synopsys and Arteris, this webinar illustrates how virtual prototyping tools and high-level architecture models provide SoC architects with deep, system-level analysis.
Pat Sheridan, Senior Staff Product Marketing Manager, Synopsys; Tim Kogel, Solution Architect, Synopsys; Alexis Boutillier, Senior Corporate Applications Engineer, Arteris
Nov 19, 2015

Optimize DDR Memory Subsystem Efficiency With Synopsys Platform Architect
A mobile device SoC subsystem case study how Platform Architect enables efficient design, performance analysis and optimization of multicore SoC architectures.
Patrick Sheridan, Senior Staff Product Marketing Manager, Synopsys; Tim Kogel, Solution Architect, Synopsys
May 05, 2015

Performance Analysis and Optimization of ARM® CoreLink™ NIC-400 based Systems
A case study demonstration of system-level performance analysis and optimization.
William Orme, Strategic Marketing Manager, Interconnect products, ARM; Patrick Sheridan, Senior Staff Product Marketing Manager, Synopsys; Tim Kogel, Solution Architect, Synopsys
May 20, 2014