14/16/20 nm and FinFET
Formal Debug: Achieving Faster Root Cause Analysis of Formal Results with VC Formal and Verdi
Based on years of hands-on experience and the latest debug features of VC Formal with Verdi, this webinar will give a practical guide to various debug techniques for analyzing formal verification results that will enable verification teams to get the most out of integrating formal verification into their flow. Using debug challenges such as assertion failures and sequential equivalence mismatches this webinar will guide users on the fastest way to a resolution. It will also show Navigator - a powerful new debug solution in Verdi – that allows quick waveform based what-if analysis on design functionality without any need for a testbench environment or assertion expertise.
Prapanna Tiwari, Senior Manager, Formal Verification Product Marketing, Synopsys; Sean Safarpour, Ph.D. Formal Verification CAE Manager, Synopsys
Sep 14, 2016

Custom Compiler-Visually-assisted Automation for Custom Layout
Learn about Synopsys' new full-custom solution that features a visually-assisted automation flow tuned for FinFET-based designs to speed up common design tasks, reduce iterations and enable reuse.
Chris Shaw, Technical Marketing Manager, Synopsys Fred Sendig, Synopsys Fellow, Synopsys
Apr 21, 2016

Design, Test & Repair Methodology for FinFET-based Memories
Understand the challenges associated with testing FinFET-based memories and new methods to address FinFET-specific defects.
Dr. Yervant Zorian, Chief Architect and Fellow, Synopsys
Mar 03, 2016

Improving Analog Verification Productivity Using Synopsys Simulation and Analysis Environment (SAE)
Learn about the comprehensive GUI-based transistor-level simulation and analysis environment that is deeply integrated with CustomSim, FineSim, and HSPICE circuit simulators.
Deepa Kannan, SAE Technical Marketing Manager, Synopsys
Feb 17, 2016

Tackle the Complexities of FinFET Library Characterization with SiliconSmart
This webinar will cover the new, innovative SiliconSmart capabilities that will enable you to work smarter in solving your toughest FinFET library characterization challenges.
Ed Lechner, Director of Marketing, Design Analysis and Sign-off Tools, Synopsys
Jan 13, 2016

TSMC/Synopsys CustomSim Collaboration for 16nm FinFET Design Success
Join TSMC and Synopsys as we discuss N16FF+/early N10 certification collaboration activities and how CustomSim 2015.06 addresses the design needs of FinFET technology nodes.
Jacob Ou, Technical Manager, TSMC; Tom Hsieh, Corporate Application Engineering Manager, Synopsys
Aug 12, 2015

Choosing the Optimal Multiprotocol PHY IP for Your SoC
Learn about the architectural differences between enterprise and consumer multiprotocol PHY and the optimal PHY solution for your SoC that meets your specific design requirements.
Rita Horner, Sr. Technical and Product Marketing Manager, Synopsys
Apr 02, 2015

Meeting 90-nm to 10-nm Physical IP Design Requirements for Wearables and Application Processors
Understand the 90-nm to 10-nm technology process and IP requirements for wearable/IoT devices and mobile application processors.
Navraj Nandra, Sr. Director of Marketing for the DesignWare Analog/Mixed Signal IP, Synopsys
Mar 31, 2015

Design, Test & Repair Methodology for FinFET-based Memories
Understand the challenges associated with testing FinFET-based memories and new methods to address FinFET-specific defects.
Dr. Yervant Zorian, Chief Architect and Fellow, Synopsys
Mar 03, 2015

FinFETs For Your Next SoC: To Move or Not To Move?
Learn about the benefits and challenges of moving from a planar CMOS process to FinFET and how DesignWare® embedded memory and logic library IP can enable this move.
Prasad Saggurti, Product Marketing Manager for Embedded Memory IP, Synopsys
Jul 22, 2014



NewsBlogsWebinarsEventsNewsletters