Performance Analysis and Optimization of ARM® CoreLink™ NIC-400 based Systems
A case study demonstration of system-level performance analysis and optimization.
William Orme, Strategic Marketing Manager, Interconnect products, ARM; Patrick Sheridan, Senior Staff Product Marketing Manager, Synopsys; Tim Kogel, Solution Architect, Synopsys
May 20, 2014

Addressing the Challenges of Multi-Protocol High Speed PHY IP in SoC Design
This webinar describes the design challenges and potential advantages of using a multi-protocol 12.5 Gbps PHY that supports a wide range of data rates, features and specifications.
Rita Horner, Product Marketing Manager, Synopsys; Paul Hua, R&D Manager, Synopsys
May 15, 2014

FineSim Technology for Analog and Full-Chip Simulation - A Micron Case Study
Learn about FineSim’s transient analysis advantage and the rich feature set that that combines SPICE and FastSPICE simulation technology in one single environment used for memory design at Micron.
Raed Sabbah, Sr. Design Engineer, Embedded Solutions Group, Micron Technology
May 08, 2014

Hybrid Emulation with ZeBu
Virtual prototypes and emulation systems not only add value in their standalone usage on large SoC projects, but can provide synergistic value when used together for performance validation, early software development and hardware verification. In this webinar we will describe the components of hybrid emulation and the principal applications of architecture analysis, software driven verification, and development of applications software.
Gwyneth Sauceda, Member Technical Staff, Verification Group, Synopsys
May 07, 2014

Increase FPGA Performance with Enhanced Capabilities of Synplify PRO and Premier
Timing is everything! Find out how to reproducibly improve FPGA performance results using Synplify Pro and Synplify Premier. This webinar includes tips on how to set up you FPGA design to achieve better timing results downstream, recommended techniques to analyze and tune design performance for faster timing closure and new "under the hood" Synplify Premier placement-aware logic synthesis technology that further boosts timing performance.
Paul Owens, Senior CAE, Synplify Business Group, Synopsys
May 06, 2014

33% Higher Design Density: Fujitsu’s Customized Flow with Design Compiler
Learn about Fujitsu’s new Customized SoC (ASIC) handoff flow with early logical and physical collaboration to improve design density, lower power and minimize iterations.
Tatsuya Nakae, Director of SoC Design Methodology Development, Fujitsu; Hitesh Patel, Product Marketing Manager, Synopsys
May 01, 2014

Counting Down to 10 nm: GLOBALFOUNDRIES and Synopsys Perspective on Future Extraction
GLOBALFOUNDRIES and Synopsys will discuss the implications for extraction as foundries move to the next level of die shrink at 10nm.
Jongwook Kye, Fellow, GLOBALFOUNDRIES; Beifang Qiu, Senior R&D Manager, Synopsys
Apr 30, 2014

Optimizing DSP cores for Performance and Power with DesignWare Logic Libraries and Embedded Memories
Learn how optimized embedded memories & logic libraries enable your DSP design to achieve performance/power/area targets, and how choosing the correct IP/methodology avoids physical design bottlenecks.
Ken Brock, Product Marketing Manager, Logic Libraries, Synopsys;Ran Snir, VLSI Director, CEVA
Apr 24, 2014

Accelerating Time to a Quality Floorplan: Cisco Systems and Synopsys Share Their Insights
Learn how IC Compiler’s new Data Flow Analysis (DFA) technology enables designers to accelerate time to a quality floorplan. Cisco Systems shares their experiences deploying this technology on a 100+ million gate ASIC to reduce floorplanning iterations with ASIC vendors and quickly identify and validate macro placement for the best quality of results.
Krishna Kumar Gundavarapu, Technical Leader, Cisco; Steve Kister, Technical Marketing Manager, Synopsys
Apr 23, 2014

Dialog Semiconductor and Synopsys Present: New DFTMAX Ultra for Squeezing Out More Test Compression with Fewer Pins
The demand for pin-limited compression is being driven by tighter form factors, the design of multicore SoCs that require few pins per core for test access, and the adoption of multisite testing as a technique to reduce test application time and cost. In this webinar, we will highlight how Synopsys’ new DFTMAX Ultra is designed from the ground up to achieve high compression using fewer digital scan pins and a minimum of one pair of scan pins. Our guest speaker will then discuss how DFTMAX Ultra is being successfully deployed to lower the cost of testing mixed-signal designs at Dialog Semiconductor.
Richard Illman, Technical Staff Member, Dialog Semiconductor; Carl Holzwarth Corporate Applications Engineering Director, Synopsys; Chris Allsup, Marketing Manager, Synopsys
Apr 17, 2014

Enrich the Multimedia Experience with HDMI 2.0 (Mandarin)
Learn about the new HDMI 2.0 specification and how it changes the landscape for multimedia SoCs and devices. Get an overview of Synopsys' HDMI 2.0 IP solution and the implementation choices available.
Tina Hu, Interface IP FAE, Synopsys
Apr 15, 2014

Case Study: Application-Specific Processors (ASIP) for the Design of Wireless SoCs
In this webinar we will use several real-world examples to highlight why ASIPs can offer computational performance close to fixed-function hardware blocks, providing instruction-level and data-level parallelism, as well as by introducing specialized hardware operators.
Markus Willems, Product Marketing Manager, Synopsys
Apr 15, 2014

ST and Synopsys Present: Synphony C Compiler for Faster Implementation of Image Processor IP
Video and image processing hardware has become pervasive in smartphones, cameras, camcorders, autos, security equipment and a host of other devices. As the algorithms often begin in C and C++, high-level synthesis (HLS) from these languages to high-quality RTL can boost design productivity by 5-10X. Our guest speaker will discuss how Synopsys’ Synphony C Compiler HLS solution is being successfully deployed to meet the challenges of designing imaging processors at STMicroelectronics. Learn how you can use Synphony C Compiler and its C++ image processing library to accelerate the delivery of your high-performance image processing IP in a fraction of the time it takes using traditional methods.
Franck Hellard, Principal Engineer, STMicroelectronics; Craig Gleason, CAE Manager, Synopsys; and Chris Allsup, Marketing Manager, Synopsys
Apr 10, 2014

The Top 5 Features to Consider when Choosing a Platform for SoC Software Development
A complete, standalone platform with all the hardware and software needed for software development, debugging, and profiling will significantly accelerate code development for SoC designs.
Allen Watson, Product Marketing Manager for ARC Development Tools, Systems and Ecosystem, Synopsys
Apr 08, 2014

Using a Golden UPF Methodology for Low Power Designs
This webinar will help you understand the best practices for implementation of a Golden UPF flow for Multi-Voltage designs using the IEEE 1801 (UPF) standard.
Somil Ingle, Sr. Corporate Applications Engineer, Synopsys; Mary Ann White, Product Marketing Director, Synopsys
Apr 03, 2014

Reducing Power Consumption in Mobile Applications with High-Speed Gear3 MIPI M-PHY IP (Mandarin)
This webinar provides an overview of the MIPI M-PHY and explains the integration challenges faced by designers while integrating M-PHY-based protocols into SoCs for Mobile Multimedia applications.
Haopeng Liu, FAE Manager, Synopsys
Mar 25, 2014

Qualcomm’s Experience: Getting Superior Results with Design Compiler 2013.12
Learn how Qualcomm, describes how Qualcomm was able to achieve superior timing, area, and power results while maintaining tight correlation to layout using Design Compiler's latest release 2013.12.
Karl Pfalzer, Implementation Architect, Qualcomm; Priti Vijayvargiya, Director of RTL Synthesis Product Marketing, Synopsys
Feb 26, 2014

Advanced Design with Smart Power BCD Technologies
Join STMicroelectronics and Synopsys as they discuss the applications of existing and upcoming smart power BCD technologies, along with design and verification solutions to help you achieve results.
Pier Luigi Rolandi, Sr. Director, Design Enablement, Technology R&D Smart Power, STMicroelectronics; Marco Casale-Rossi, Product Marketing Manager, Implementation Group, Synopsys
Feb 20, 2014

Easy and Intuitive Analysis of Design Metrics with the Lynx Design System's QoR Viewer
Immediate access to pertinent design metrics enables better design decisions and faster time to results. Learn how Lynx enables you to customize metric review to highlight key data material to achieving design goals.
Aditya Ramachandran, Lynx Design System Staff CAE, Synopsys
Feb 19, 2014

Enrich the Multimedia Experience with HDMI 2.0
Learn about the new HDMI 2.0 specification and how it offers consumers the ultimate home theater experience. This webinar describes the HDMI 2.0 specification, compares it to previous version, and details its new audio, video, and security features.
Manmeet Walia, Senior Product Marketing Manager for DesignWare HDMI IP, Synopsys
Jan 30, 2014

Streamlining IP and Subsystem Prototyping with HAPS-DX
In this webinar we will introduce the new HAPS Developer eXpress (HAPS-DX) solution for complex IP and subsystem prototyping to accelerate IP and subsystem bring-up and streamline IP to SoC integration.
Neil Songcuan, Senior Product Marketing Manager, Synopsys
Jan 29, 2014

Reducing Power Consumption in Mobile Applications with High-Speed Gear 3 MIPI M-PHY IP
This webinar provides an overview of the MIPI M-PHY and explains the integration challenges faced by designers while integrating M-PHY-based protocols into SoCs.
Hezi Saar, Product Marketing Manager for DesignWare MIPI IP, Synopsys
Jan 22, 2014

Scaling ADC Architectures for Mobile & Multimedia SoCs at 28-nm & Beyond (Mandarin)
Learn about the main analog-to-digital converter (ADC) architectures, how the Successive-Approximation Register (SAR)-based ADC architecture is ideal for ADC implementation in 28nm process nodes and beyond and how it exploits the high speed and high processing power offered by these advanced process technologies.
Ming Han, FAE for Analog IP, Synopsys
Jan 14, 2014

Fastest Multi-scenario Timing Closure with PrimeTime Physically-aware ECO - AMD Shares Results (Simplified Chinese)
AMD and Synopsys will discuss the latest enhancements to PrimeTime's ECO Guidance technology to accelerate multi-scenario timing closure.
James Wai, Director of Physical Design, AMD; Chung Yang, Staff CAE, Synopsys
Dec 19, 2013