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Seminar Series 2010
Attend a Synopsys technical seminar near you
Webinars
View our online webinars and learn from technology experts on a variety of topics.
SNUG Conferences
Forum for Synopsys users to exchange, discuss and explore ideas
Workshop Series 2010
Hands-on learning from Synopsys experts
News
Yamaha Tapes Out Their Latest Graphics LSI Chip with Synopsys Design Compiler Graphical
Synopsys to Acquire CoWare, Inc.
APAC IC Adopts Synopsys Galaxy Custom Designer Solution to Meet Growing Analog/Mixed-Signal IC Design Service Demand
Synopsys Announces Earnings Release Date and Conference Call for the First Quarter Fiscal Year 2010
Synopsys Acquires VaST Systems Technology Corporation
Aeroflex Realizes 60x Performance Improvement Using Synopsys CustomSim Solution
Synopsys Showcases Silicon-Proven DesignWare IP Solutions for SuperSpeed USB 3.0, DDR and PCI Express at DesignCon 2010
Synopsys Offers Designers Many Opportunities for Design Success at EDSFair
Toshiba Information Systems (Japan) Standardizes on VMM-LP Low Power Verification Methodology
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Blogs
Low Power Blog: Magic Blue Smoke
A View from the Top: A System-Level Blog
AMS Verification Blog: Analog Insights
On Verification: A Software-to-Silicon Verification Blog
Standards Blog: The Standards Game
USB IP Blog: To USB or Not to USB
The Eyes Have it: An IP Blog
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Webinars
The Big Design Squeeze: speeding FPGA design
3-D TCAD Simulation with Sentaurus
Reducing Design Margins Using Advanced OCV
DesignWare IP for AMBA 3 AXI On-Chip Bus
Transaction-level Debug Using VCS
Signal Integrity Noise in Low Power Design
Low Power Algorithm Exploration
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Events
SPIE Advanced Lithography
DVCon 2010
DATE 2010
ISQED 2010
ISETC 2010
SNUG San Jose
Photomask Japan
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Press Room
Investor Relations
About Synopsys
Office Locations
Publications
A
AMBA
AMS Co-Sim
Audio IP
C
Cadabra
CATS
Certify
CHIPit.com
Circuit Check
Confirma
coreAssembler
coreBuilder
coreConsultant
Custom Designer LE
Custom Designer SDL
Custom Designer SE
Custom WaveView
CustomExplorer
CustomSim
D
Data Converters
Datapath
DC Ultra
DDR
Design Compiler Graphical
Design Services
DesignWare
DesignWare System-Level Library
Device Controller
DFTMAX
DSP model libraries
E
Eclypse Low Power Solution
ESP-CV
Ethernet
F
Fammos TX
Formality
FPGA Design
G
Galaxy Constraint Analyzer
H
HAPS
HDMI IP
Hercules
HSIM
HSIM Plus
HSPICE
I
I2C
IC Compiler
IC Validator
IC Workbench Plus
Identify
Identify Pro
Implementation
Innovator
Interconnect Simulation
IP
J
JPEG
L
Leda
Liberty NCX
Lynx Design System
M
Magellan
Manufacturing
Memory Models
M
Microcontrollers
Mobile Storage
MVRC Multi-voltage Rule Checker
MVSIM
N
NanoSim
NanoTime
O
OCP
Odyssey
P
PCI Express
PCI/PCI-X
Pioneer-NTB with Vera
Power Compiler
PrimeRail
PrimeTime
PrimeYield
Process Simulation
Proteus
Proteus MetroKit
PSM-Check and Create
R
Raphael
Raphael NXT
S
Saber
Saber Harness
Saber Simulator
SATA
Seismos CX
Seismos LX
Sentaurus Device
Sentaurus Lithography
Sentaurus Process
Sentaurus Topography
Serial I/O
Signoff
SiVL
SRAMs
Star IP
StarRC
Synplify DSP
Synplify Premier
Synplify Pro
System Level Library
System Studio
T
Taurus-Medici
Taurus-TSuprem4
TCAD
TetraMAX ATPG
Touch Screen Controllers
U
USB
V
VCS
VCS Verification Library
Verification
Verification IP
Video Analog Front Ends
Virtual Platforms
W
Wireless USB
X
XA Technology
XAUI
Y
Yield Explorer
Z
Zroute
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