Synopsys University Symposium  

SoC Architecture Design & Embedded Software Development with Virtual Prototyping 

Thursday, April 30th
9:00 a.m. to 5:30 p.m.
Shangri-La's - Eros Hotel

19 Ashoka Road, Connaught Place
New Delhi 110001

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This FREE technical symposium is for members of the academic community to get the latest information on design automation solutions, methodologies and standards. Join us to learn how you can achieve the highest value and productivity from your Synopsys tool investment.

SoC Architecture Design and Embedded Software Development with Virtual Prototyping

SoCs are getting increasingly complex and together with time to market pressures are rendering the traditional design methods ineffective. Most of the SoCs today have multiple cores, complex cache coherent architectures, complex clock, reset and power management circuits, specialized IP’s and very high amounts of embedded software content. This calls for tremendous innovation in the design process for companies to stay competitive.

Virtual Prototyping tools have emerged as a viable solution to provide designers the ability to analyze and explore architectures to meet the stringent power and performance needs, accelerate embedded software development and debug through early prototypes. This seminar will provide professors and researchers with a conceptual understanding of virtual prototyping and how to leverage these to start before hardware is available.

Who Should Attend

  • Faculty & Research Scholar focusing on system design and implementation
  • Research groups focused on product design


9:00 – 9:30 a.m.Registration Check-In
9:30 – 9:45 a.m.Welcome and Synopsys India University Program Overview
Gunjan Singh, Synopsys
9:45 – 10:45 a.m.Performance Proof Points and Correlation Across System on Chip Design Cycle
Baljinder Sood, Freescale
10:45 – 11:00 a.m.Tea Break
11:00 – 1:00 p.m.Introduction to Virtual Prototyping & Use Cases
Architecture Exploration, Design & Optimization, Enabling Early Software Development
Ashwani Aggarwal & Neeraj Goel, Synopsys
1:00 – 2:00 p.m.Lunch
2:00 – 3:00pmMemory Architecture Reconfiguration and Exploration
Prof. Preeti Ranjan Panda, IIT Delhi
3:00 – 4:00 p.m.An Introduction to Application Specific IP Design
Ashutosh Pal, Synopsys
4:00 – 4:45 p.m.Panel Discussion
4:45 – 5:00 p.m.Lucky Draw

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Attendance at this event is free, but registration is required.

Hosted in conjunction with Eigen Technologies Pvt. Ltd, New Delhi, +91-11-41643004