Synopsys announces the first Analog Design Contest featuring Synopsys Custom Design tools.
Contestants will receive free training with Synopsys industry-standard analog IC design tools and will have the opportunity to engage with industry experts in analog design.
Congratulations to the following teams for making it to the final round!
- Jeetesh Chaturvedi & Dhiraj Kumar from ABV-IIITM, Gwalior
- Pratosh Kumar Pal & Anjani Kumar Singh from ABV-IIITM, Gwalior
- Piyush Verma & Shailendra Singh Tomar from Bharati Vidyapeeth's College Of Engineering, New Delhi
- Som Singh Chauhan & Manish Yadav from JSS College - UPTU-Lucknow
- Karthiyayini N & Mehanathan S from College of Engineering, Anna University
- Mohammed Abdul Hannan & Hamza Saleem Ahmed from Muffakham Jah College of Engineering and Technology
- Ankur Debnath & Subhankar Sarkar from National Institute of Technology, Agartala
- Susmita Majumder & Debanjali Nath from National Institute of Technology, Agartala
- Bharadwaj Lingam & Sree Gowtham J from NITK Surathkal
- G Akshay Kumar & Chougoni Shyam Prasad Gowd from NITK Surathkal
- Kiran Patil & Rahul Bire from Yeshwantrao Chavan College of Engineering
- Contest Design & Rules:
- Teams will design a complete schematic and DRC/LVS clean layout of a low-dropout voltage regulator as per given specifications using only Synopsys provided analog mixed signal tools.
- All designs submitted must be original work – designed and drawn by the contestants for this contest. Designs may not have been previously used or directly copied from other sources. This will result in immediate team disqualification.
- Teams are required to use the interoperable PDK provided by Synopsys for the competition.
- Project submissions will be evaluated by the contest committee members and judged based on the following criteria, which includes but is not limited to:
- Functionality demonstrated through HSPICE simulations
- Measure of efficiency, drop-out voltage, quiescent current, load regulation, line regulation, and Power Supply Rejection Ratio (PSRR)
- Optimal area of layout that is DRC/LVS clean
- Effective use of design productivity features available with the tool flow
All judging decisions made by the contest committee members will be final.
|Last Day to Nominate Teams
||April 20, 2014
|Design Briefing & Tools/Methodology Training*
||May 28 – 30 at CDAC, Noida
June 11 – 13 at Synopsys, Hyderabad
June 16 – 18 at Synopsys, Hyderabad
June 18 – 20 at CDAC, Noida
|First Reports Due
||August 10, 2014
|Qualifiers of Final Round Notified
||August 22, 2014
|Final Round Schematics, Layouts, and Reports Due
||September 28, 2014
||October 5, 2014
|Prizes Awarded at University Symposium in Bangalore
* Teams only need to attend one training session.
University of Hyderabad
Contest Committee Members:
|Dr. P A Govindacharyulu
Vasavi College of Engg
|Suresh Kumar Gourabathuni
Manager , R&D, Solutions Group
|Venkata Reddy Sanamreddy
R&D Engr., Solutions Group
Director, Analog Solutions Group
Sankalp Semiconductor, Kolkata
|Uno V. Nellore
Mgr., Tech Support & Training
For additional information contact firstname.lastname@example.org