Deadline to Nominate Teams has passed.
Synopsys announces the first Analog Design Contest featuring Synopsys Custom Design tools.
Contestants will receive free training with Synopsys industry-standard analog IC design tools and have the opportunity engage with industry experts in analog design.
- Who can be nominated:
- Bachelor or Masters engineering students in their final year, 2014-2015, attending any University/Educational Institute located in India.
- Maximum of four students per institute. Each institute may nominate two teams consisting of two students per team.
- Team nominations must be submitted by a designated faculty member or Head of Department at any University/Educational Institute in India.
- Contest Design & Rules:
- Teams will design a complete schematic and DRC/LVS clean layout of a low-dropout voltage regulator as per given specifications using only Synopsys provided analog mixed signal tools.
- All designs submitted must be original work – designed and drawn by the contestants for this contest. Designs may not have been previously used or directly copied from other sources. This will result in immediate team disqualification.
- Teams are required to use the interoperable PDK provided by Synopsys for the competition.
- Project submissions will be evaluated by the contest committee members and judged based on the following criteria, which includes but is not limited to:
- Functionality demonstrated through HSPICE simulations
- Measure of efficiency, drop-out voltage, quiescent current, load regulation, line regulation, and Power Supply Rejection Ratio (PSRR)
- Optimal area of layout that is DRC/LVS clean
- Effective use of design productivity features available with the tool flow
All judging decisions made by the contest committee members will be final.
|Last Day to Nominate Teams||April 20, 2014|
|Design Briefing & Tools/Methodology Training*||May 28 – 30 at CDAC, Noida|
June 11 – 13 at Synopsys, Hyderabad
June 16 – 18 at Synopsys, Hyderabad
June 18 – 20 at CDAC, Noida
|First Reports Due||August 10, 2014 |
|Qualifiers of Final Round Notified ||August 22, 2014 |
|Final Round Reports Due||September 28, 2014 |
|Winner Announced||October 3, 2014|
|Prizes Awarded at University Symposium in Bangalore||October 2014|
* Teams only need to attend one training session.
University of Hyderabad
Contest Committee Members:
|Dr. P A Govindacharyulu|
Vasavi College of Engg
|Suresh Kumar Gourabathuni |
Manager , R&D, Solutions Group
|Arti Noor |
|Venkata Reddy Sanamreddy|
R&D Engr., Solutions Group
Director, Analog Solutions Group
Sankalp Semiconductor, Kolkata
|Uno V. Nellore|
Mgr., Tech Support & Training
For additional information contact email@example.com