DAC 2013 

Speakers 

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WEDNESDAY, JUNE 5

PAPER SESSION 23:
Huff and PUF
Topic Area: Embedded System Validation and Verification
Time: 9:00 a.m. to 10:30 a.m.
Location: Room 11AB

First, we build systems for speed and efficiency. Then, we spend a lot of time worrying about how safe and secure they are. Can we change this thought process? What if we built systems that were reliable and secure in the first place? What if we make security and resilience themes in our chip design, instead of time to market? Come think of these and other mind bending ways to design the next generation of chips! With physically unclonable functions, verification mechanisms for ensuring trust in hardware and spatio-temporal error tolerance for processors, this session will tickle your grey cells!
Chair: Sashi Obilisetty, Synopsys, Mountain View, CA

PAPER SESSION 25.1:
Machine-Learning-Based Hotspot Detection Using Topological Classification and Critical Feature Extraction
Topic Area: Analog/Mixed-Signal
Time: 9:00 a.m. to 10:30 a.m.
Location: Room 14

This section will show case advances in lithography. This paper on hot spot detection by machine will show how this approach has high accuracy and low false alarm.

Speaker:
  • Yen-Ting Yu, National Chiao Tung Univ., Hsinchu, Taiwan
Authors:
  • Yen-Ting Yu, National Chiao Tung Univ., Hsinchu, Taiwan
  • Geng-He Lin, National Chiao Tung Univ., Hsinchu, Taiwan
  • Iris Hui-Ru Jiang, National Chiao Tung Univ., Hsinchu, Taiwan
  • Charles Chiang , Synopsys, Inc., Mountain View, CA

PAPER SESSION 32.4:
Spacer-Is-Dielectric-Compliant Detailed Routing for Self-Aligned Double Patterning Lithography (Best paper candidate)
Topic Area: Physical Design
Time: 1:30 p.m. to 3:00 p.m.
Location: Room 15

Design sizes are exploding. The complexity of the wire stack is increasing. Design rules are numbingly complex. The importance of routing and clock network synthesis in this environment has never been more critical. But never fear, there's a party going on right here. This session addresses issues in clock skew variation, clock power, routing congestion estimation for real world designs, and spacer-is-dielectric-compliant detailed routing. Come route around the clock with us!

Moderator:
  • Mehmet Yildiz, Synopsys, Inc., Austin, TX
Speaker:
  • Yuelin Du, Univ. of Illinois at Urbana-Champaign, Urbana, IL
Authors:
  • Yuelin Du, Univ. of Illinois at Urbana-Champaign, Urbana, IL
  • Martin D. F. Wong, Univ. of Illinois at Urbana-Champaign, Urbana, IL
  • Qiang Ma, Synopsys, Inc., Mountain View, CA
  • Hua Song, Synopsys, Inc., Mountain View, CA
  • James Shiely, Synopsys, Inc., Hillsboro, OR
  • Gerard Luk-Pat, Synopsys, Inc., Mountain View, CA
  • Alexander Miloslavsky, Synopsys, Inc., Mountain View, CA

TECHNICAL PANEL 34:
EDA: Meet Analytics; Analytics: Meet EDA
Topic Area: Emerging Technologies
Time: 4:00 p.m. to 5:30 p.m.
Location: Room 16AB

The sheer scale of data generated by EDA tools used on a system-on-chip (SoC) suggest that analytics should play a major role in speedy SoC completion. This is especially true for functional verification where analytics can be helpful in sizing the problem, assessing progress, and improving process. However, beyond familiar coverage metrics, this is not the case today. This panel considers statistical analysis, data mining, machine learning, and other analytic methods to gain more insight into verification—and whether the analytics approach can extend to other SoC design areas.

Moderator:
  • Janick Bergeron, Synopsys, Inc., Ottawa, ON, Canada
Panelists:
  • Jay Bhadra, Freescale Semiconductor, Inc., Austin, TX
  • Harry Foster, Mentor Graphics Corp., Plano, TX
  • Li-C Wang, Univ. of California, Santa Barbara, CA
  • Avi Ziv, IBM Haifa Research Lab., Haifa, Israel
  • Fei Xie, Portland State Univ., Portland, OR


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