DAC 2013 

Speakers 

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TUESDAY, JUNE 4

PAPER SESSION 4.1:
Double-Patterning Lithography-Aware Analog Placement
Topic Area: Analog/Mixed-Signal
Time: 10:30 a.m. to 12:00 p.m.
Location: Room 13AB

What's up with analog layout? This session focuses on new challenges for emerging analog and mixed-signal (AMS) circuit technologies. This papers proposes a novel physical design solutions for nanoscale AMS circuits that improve printability and matching while reducing coupling.

Speaker:
  • Hsing-Chih Chang Chien, National Taiwan Univ., Taipei, Taiwan
Authors:
  • Hsing-Chih Chang Chien, National Taiwan Univ., Taipei, Taiwan
  • Hung-Chih Ou, National Taiwan Univ., Taipei, Taiwan
  • Tung-Chieh Chen, Synopsys, Inc., Hsinchu, Taiwan
  • Ta-Yu Kuan, Synopsys, Inc., Hsinchu, Taiwan
  • Yao-Wen Chang,National Taiwan Univ., Taipei, Taiwan

MANAGEMENT DAY:
DAC Management Day 2013
Topic Area: General Interest
Time: 10:30 a.m. to 6:00 p.m.
Location: Room 17AB

DAC Management Day 2013 provides managers with timely information to help them make decision where business and technology intersect. This is a unique opportunity for manager to gain insights.

Organizer:
  • Yervant Zorian, Synopsys, Inc., Mountain View, CA

PAPER SESSION 11.3:
Automatic Design Rule Correction in the Presence of Multiple Grids and Track Patterns
Topic Area: Physical Design
Time: 1:30 p.m. to 3:00 p.m.
Location: Room 14

Technology scaling into the 14nm node and beyond brings many new challenges to physical design algorithms and optimization. In this new world, FinFET devices, E-Beam lithography, design rule corrections and 3D design planning are all essential to succeeding designing in advance technology nodes. Put your fears aside in this session as you learn about techniques for addressing these modern physical design challenges.

Speaker:
  • Nitin D. Salodkar, Synopsys (India) Pvt. Ltd., Bangalore, India
Authors:
  • Nitin D. Salodkar, Synopsys (India) Pvt. Ltd., Bangalore, India
  • Subramanian Rajagopalan, Synopsys (India) Pvt. Ltd., Bangalore, India
  • Sambuddha Bhattacharya, Synopsys (India) Pvt. Ltd., Bangalore, India
  • Shabbir H. Batterywala, Synopsys (India) Pvt. Ltd., Bangalore, India

PAPER SESSION 12.4:
An ATE-Assisted DFD Technique for Volume Diagnosis of Scan Chains (Best paper candidate)
Topic Area: Test and Reliability
Time: 1:30 p.m. to 3:00 p.m.
Location: Room 15

Bug-free design and defect-free fabrication are nearly impossible. Design and silicon imperfections are exposed using a parallelized test generation algorithm, a virtual machine-based silicon validation, and elegant approaches for isolating defects in test-access and error-recovery logic.

Speaker:
  • Subhadip Kundu, Indian Institute of Technology, Kharagpur, India
Authors:
  • Subhadip Kundu, Indian Institute of Technology, Kharagpur, India
  • Santanu Chattopadhyay, Indian Institute of Technology, Kharagpur, India
  • Indranil Sengupta, Indian Institute of Technology, Kharagpur, India
  • Rohit Kapur, Synopsys, Inc., Mountain View, CA


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