DAC 2013 


Sunday | Monday | Tuesday | Wednesday | Thursday


Analog Design with FinFETs: "The Gods Must be Crazy!"
Topic Area: Analog/Mixed-Signal
Time: 1:30 p.m. to 2:30 p.m.
Location: Room 16AB

FinFET devices have emerged as the winner for process nodes beyond 20nm. The advantages are too compelling to ignore. However what's great for SoC is a real challenge for analog. With sub-threshold currents near zero and virtually no bias control capability, suddenly the analog designer will have to throw out the old schematics and really start to rethink the problem. The big question: How quickly will mainstream analog design find its way into FinFET-driven logic processes?

  • Ron Wilson, Altera Corp., San Jose, CA
  • Anirudh Devgan, Cadence Design Systems, Inc., Austin, TX
  • Scott Herrin, Freescale Semiconductor, Inc., Austin, TX
  • Navraj Nandra, Synopsys, Inc., Mountain View, CA
  • Eric Soenen, Taiwan Semiconductor Manufacturing Co., Ltd., Austin, TX

Routability-Driven Placement for Hierarchical Mixed-Size Circuit Designs
Topic Area: Physical Design
Time: 1:30 p.m. to 3:00 p.m.
Location: Room 14

"Houston, we have a routability problem." We have great solutions for you in Austin! The landscape of placement research has shifted significantly in recent years. The research community has realized that a pure wirelength objective does not solve the real physical design challenge. Routability has become a "must" in placement research. Watch the launch of the next generation of placement innovations.

  • Meng-Kai Hsu, National Taiwan Univ., Taipei, Taiwan
  • Meng-Kai Hsu, National Taiwan Univ., Taipei, Taiwan
  • Yi-Fang Chen, National Taiwan Univ., Taipei, Taiwan
  • Chau-Chin Huang, National Taiwan Univ., Taipei, Taiwan
  • Tung-Chieh Chen, Synopsys, Inc., Hsinchu, Taiwan
  • Yao-Wen Chang, National Taiwan Univ., Taipei, Taiwan

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