DAC 2013 

Partners and Standards 

ARM Connected Village
Booth #921

Overview Demonstrations
Daily; 9:00 a.m. – 6:00 p.m.
Learn more about Synopsys’ implementation, verification, systems and ARM-Synopsys collaboration efforts.

ARM-TSMC-Synopsys Breakfast
Optimizing Implementation of Performance- and Power-Balanced Processor Cores
Monday, June 3, 2013; 7:15 a.m. – 8:45 a.m.
Hilton Hotel, Grand Ballroom H
Learn about the latest Synopsys technologies that can be used to efficiently optimize the implementation of ARM® Cortex®-A15 and Cortex-A7 cores to meet power and performance targets.

Theater Presentation
Optimizing and Validating the Performance of an AMBA® 4-based Cache-coherent Interconnect
Wednesday, June 5, 2013; 9:40 a.m. – 10:10 a.m.
Booth 921 Theater
Learn how engineers can address the challenges associated with the performance of cache-coherent AMBA4 interconnects from two perspectives using a case study of a server SoC. First we will show how system architects can explore the architecture performance, power, and cost at a high level to narrow down the architecture to a final specification for RTL design. Then we will show how the performance of the RTL implementation is validated against the earlier performance results.


Booth #1314

Technical Seminar
Achieve Higher Yield, Faster Ramp With Yield Explorer
Monday, June 3, 2013; Noon to 1:00 p.m. (includes lunch)
Booth 1314 meeting room
Learn how Yield Explorer accelerates yield ramp by bringing together design, fab, and test data to enable a fast and efficient methodology to quantify and calibrate the effect of hotspots and inline defect measurements on yield and scan diagnostics.
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Technical Seminar
Xceptional IP for GLOBALFOUNDRIES 14nm-XM Technology
Monday, June 3, 2013; 2:00 p.m. to 3:00 p.m.
Booth 1314 meeting room
Join this session to hear how Synopsys is partnering with GLOBALFOUNDRIES to deliver high-quality DesignWare® Embedded Memory and Logic Libraries for GLOBALFOUNDRIES’ 14nm-XM technology, helping designers achieve their performance, power and area targets. Also learn more about Synopsys’ broad IP portfolio supporting GLOBALFOUNDRIES from 65- to 28-nm processes.
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Theater Presentation
Foundry Reference Flow Ecosystem Empowers Designers to Achieve Aggressive Time-to-Market Challenges
Monday, June 3, 2013; 1:45 p.m. – 2:00 p.m.
Booth 1314 Theater

GLOBALFOUNDRIES-Synopsys Breakfast
Ready for Deploying 14XM FinFETs in Your Next Mobile SoC Design
Tuesday, June 4, 2013; 7:15 a.m. – 8:45 a.m.
Hilton Hotel, Grand Ballroom G
Experts from GLOBALFOUNDRIES and Synopsys will describe the key FinFET design advantages and challenges, and share how they are collaborating on silicon, IP and design tools flows enablement to address these challenges

Technical Seminar
Accelerating GLOBALFOUNDRIES 14nm-XM FinFET Adoption Through Collaboration
Tuesday, June 4, 2013; 1:00 p.m. – 2:00 p.m.
Booth 1314 meeting room
Learn how GLOBALFOUNDRIES and Synopsys are collaborating together on process development and performance optimization of FinFET devices. Additionally, find out how Synopsys’ implementation products (including parasitic extraction, SPICE modeling, analysis) and IP development are all FinFET-ready for GLOBALFOUNDRIES’ 14nm-XM process, ensuring your design teams’ smooth adoption and transition to FinFET-based technology design.
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Theater Presentation
Synopsys/GLOBALFOUNDRIES Collaboration on Interoperable PDK Enablement
Tuesday, June 4, 2013; 4:45 p.m. – 5:00 p.m.
Wednesday, June 5, 2013; 10:45 a.m. – 11:00 a.m.
Booth 1314 Theater


Theater Presentation
Galaxy Innovations and Collaboration with Samsung for 14-nm FinFET Success
Monday, June 3, 2013; 4:30 p.m. – 4:45 p.m.
Wednesday, June 5, 2013; 10:30 a.m. – 10:45 a.m.
Booth 915 Theater

Theater Presentation
Accelerating SoC Designs with Synopsys DesignWare® IP for Samsung Processes
Tuesday, June 4, 2013; 1:30 p.m. – 1:45 p.m.
Booth 915 Theater

Theater Presentation
Enabling Advanced SoC Designs for TSMC Processes with DesignWare IP
Wednesday, June 5, 2013; 10:30 a.m. – 10:45 a.m.
Booth 915 Theater


Theater Presentation
Custom Design with Laker at 20-nm and Below
Monday, June 3, 2013; 11:30 a.m.
Booth 1736


TSMC Open Innovation Platform
Booth #1746

ARM-TSMC-Synopsys Breakfast
Optimizing Implementation of Performance- and Power-Balanced Processor Cores
Monday, June 3, 2013; 7:15 a.m. – 8:45 a.m.
Hilton Hotel, Grand Ballroom H
Learn about the latest Synopsys technologies that can be used to efficiently optimize the implementation of ARM® Cortex®-A15 and Cortex-A7 cores to meet power and performance targets.

Enabling Advanced SoC Designs for TSMC Processes with DesignWare IP
Monday, June 3, 2013; 4:30 p.m.
TSMC Booth 1746 Theater

Synopsys’ Galaxy Solution for TSMC 16-nm FinFET Enablement
Wednesday, June 5, 2013; 9:45 a.m.
TSMC Booth 1746 Theater

Custom Design with Laker at 20-nm and Below
Wednesday, June 5, 2013; 1:45 p.m.
TSMC Booth 1746 Theater


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