DAC 2013 

Demo Descriptions 
  • Design Compiler: Accelerate Your RTL Exploration and Implementation
    Join this session to hear about new capabilities in DC Explorer that expedite turnaround time, such as the pre-synthesis link to IC Compiler floorplanning for early design exploration. Get a preview of how you can analyze your design early in the design cycle and cross-probe to RTL for improving RTL quality. Additionally, learn about advances in Design Compiler Graphical that deliver higher frequency, lower power and better circuit quality for faster design closure.
  • Functional Verification: A Comprehensive Solution for Addressing Rising SoC Challenges
    This demo provides an overview of Synopsys' functional verification platform and new technologies to help leading design teams manage verification complexity. Synopsys experts demonstrate high-performance simulation methodologies, advanced debug automation, native SystemVerilog Verification IP, transaction-based verification with hardware assistance, FPGA prototyping, and the latest advancements in analog/mixed signal, low-power and system-level verification solutions to help improve verification productivity.
  • IC Compiler: Enabling Advanced Designs at All Process Nodes
    Learn how IC Compiler's latest technology addresses the advanced needs of designers at both the emerging process nodes and the established process nodes. This session covers IC Compiler's Data Flow Analysis technology and the new Concurrent Clock and Data capability. These technologies enable faster turnaround time and higher quality-of-results for predictable design closure at all process nodes.
  • IC Compiler Custom Co-Design: Seamless Roundtrip Implementation
    Learn how IC Compiler Custom Co-Design accelerates the SoC design cycle by enabling quick and reliable custom edits to IC Compiler designs at any stage of development. IC Compiler Custom Co-Design enables higher productivity through advanced features, such as DRC-/LVS-correct interactive auto-routing for shielded nets, differential pairs, matched auto-routing and automatic DRC correction technology. Synopsys' unified implementation solution enables design teams to easily move between digital and custom implementation flows while maintaining design data integrity.
  • PrimeTime: Latest Advances in Timing Signoff
    Learn how Synopsys’ advancements in physically-aware ECO enables the fastest way to timing closure with proven PrimeTime signoff working together with strong place-and-route technology in IC Compiler. Additionally, learn about Synopsys’ latest performance and modeling innovations in STA and extraction technologies enabling PrimeTime and StarRC to remain the cornerstone of signoff flows at advanced process nodes.
  • Synopsys Custom Design Solution
    Learn about the latest advances in Synopsys’ custom IC solution based on the Laker custom design tool. The flow will highlight the layout automation technologies in Laker and its integration in the Galaxy Platform. The full flow will be illustrated from schematic capture, using the Custom Designer schematic editor, through simulation, layout and final verification of a typical analog design. We show how easy Laker makes it to speed through complex analog layout. We also show how Laker provides full support for advanced-node requirements, such as double-patterning and FinFET devices.

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