DAC 2012 

Speakers 

Monday | Tuesday | Wednesday | Thursday

WEDNESDAY, JUNE 6

PAVILION PANEL
Town Hall: Dark Side of Moore's Law
Topic Area: Business
Time: 9:15 AM - 10:15 AM
Location: Booth #310
Speakers: John Chilton, Senior Vice President

Summary
Semiconductor companies double transistor counts every 22 months, yet device prices stay relatively the same. This has been a windfall for customers but not for chip makers, who have exponentially increasing design costs every new cycle. Venture capitalist Lucio Lanza and panelists will discuss what it will take to bring design costs and profitability back into harmony with Moore’s Law.

SESSION 27: RESEARCH PAPER SESSION
Design, the Next Generation: From Routing to Capturing Design Expertise
Topic Area: Physical Design
Time: 1:30 PM - 3:00 PM
Location: 300
Speakers: Charles Chiang, Synopsys Scientist

Summary
A bottleneck for complex designs is routing: the wiring of billion-gate designs is staggeringly complex, and the problem will only get worse. Routing solutions must be high quality, meeting timing and manufacturability constraints. This session provides strides forward on some of today's most important challenges, with triple patterning innovations, more accurate routability estimation, SAT-based cell routing for higher quality, and a novel obstacle-avoiding rectilinear Steiner tree approach for multiple layers. As the industry hurtles forward with process technology, routing remains the critical step. The last paper, both a historical and futuristic perspective, addresses increasing design complexity by embedding designer knowledge into systems we create, calling for creating constructors, and not design instances.

SESSION 25: PANEL
Is EDA in the Cloud Just Pie in the Sky?
Topic Area: Business
Time: 1:30 PM - 3:00 PM
Location: 305
Speakers: Bruce Jewett, Sr. Director Marketing

Summary
Promises of lower costs, seemingly infinite resources, and faster turnaround times make EDA in the cloud an attractive proposition, but skepticism is prevalent. Some object that EDA in the cloud is not new and failed a decade ago. Others worry about security, confidentiality, and data protection. Do traditional time-based licenses fit in this model? Find out whether design in the cloud is ready for primetime.

Chip Estimate Booth # 1202
DesignWare IP: A Proven Path to Silicon Success
Topic Area: IP
Time: 3:30PM
Location: Booth #1202

Summary
Learn how the latest development in DesignWare IP can help you integrate needed functionality into your SoC designs with less risk and improved time-to-volume. Hear about new products and features such as the multi-gear MIPI M-PHY supporting six protocols, HDMI 1.4 RX fast-switching capabilities, and optimized embedded memories and logic libraries for 28-nm process. In addition, get the latest product updates on USB 3.0, PCI Express 3.0, DDR, analog IP and more.

SESSION 31: PANEL
Hot Apps, Cool Phones: Power-Efficient Mobile Design
Topic Area: Low-Power Design and Power Analysis
Time: 4:00 PM - 6:00 PM
Location: 305
Speakers: Alan Gibbons, Solution Architect

Summary
Recently, we have focused on techniques for low-power hardware design. But it is not enough. With the advent of app-driven mobile devices, battery life is paramount. We must now consider the impact of software on power consumption, and the EDA industry must look to providing environments that enable modeling, measuring and optimizing the impact of hardware and software interaction on power consumption at the system level. Our panelists explore the technical challenges and potential solutions for designing and verifying these complex power efficient systems.

SESSION 33: RESEARCH PAPER SESSION
The Right Placement at the Right Timing
Topic Area: Physical Design
Time: 4:00 PM - 6:00 PM
Location: 300
Speakers: Saurabh Adya , R&D Engineer

Summary
Great chips need great placements; without this, little else matters. The papers in this session push the state of the art forward, leveraging stacked TSVs to improve cooling, and better numerical techniques for analytic placement. Underlying structure and regularity is deciphered, giving new ways to tame large designs. The session concludes with new benchmarks and metrics for placement, and the results of the 2012 DAC placement contest, where teams from around the world compete head-to-head for the title of Best Placer Ever.


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