DAC 2012 

Speakers 

Monday | Tuesday | Wednesday | Thursday

TUESDAY, JUNE 5

PAVILION PANEL
Foundry, EDA and IP: Solve Time-to-Market Already!
Topic Area: IP
Time: 11:30 AM - 12:15 PM
Location: Booth #310
Moderator: Ron Wilson - Altera Corp., San Jose Ca.
Speakers: Dr. Naveed Sherwani - Open Silicon, Inc. Milpitas, CA
Kevin Meye - GLOBALFOUNDRIES, Milpitas, CA
John Koeter, Vice President of Marketing, Mountian View, CA

Summary
Designing billion+ transistor SoCs for 20nm and below in 22 months is not fast enough! Challenges include qualifying and integrating IP blocks, custom logic, and achieving design closure. This panel will discuss what foundry, IP and EDA vendors are doing to step up and finally deliver plug-and-play solutions.

PAVILION PANEL
Conquering New Frontiers in Analog Design – Plunging Below 28nm
Topic Area: Analog/Mixed-Signal/RF Design
Time: 4:00 PM - 4:45 PM
Location: Booth #310
Speakers: KT Moore, Director Product Marketing

Summary
Analog design flows have not changed much in the past two decades, yet analog IP has been at the forefront of every new technology node breakthrough.  This panel will discuss some of the major electrical, physical and process design challenges at 28nm and below, and what adjustments can be made in the design ecosystem to facilitate first-pass silicon success.

Chip Estimate Booth # 1202
Audio IP Subsystems Made Easy with an Integrated, SoC Ready Solution
Topic Area: IP
Time: 4:00 PM
Location: Booth # 1202

Summary
The trend towards internet-connected consumer devices is driving an increase in the audio requirements and complexity of today's SoCs. These designs need to support elements such as multi-channel, high-definition audio formats as well as plug seamlessly into the host application software. Designers are turning to dedicated audio subsystems to off-load the audio processing from the host processor, thus reducing design complexity and improving the performance and efficiency of the SoC. Learn how a how a pre-verified, integrated audio IP subsystem solution, consisting of hardware, software and prototypes reduces integration effort, lowers risk and accelerates time-to-market.


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