DAC 2012 

Speakers 

Monday | Tuesday | Wednesday | Thursday

THURSDAY, JUNE 7

SESSION 45: RESEARCH PAPER SESSION
Surviving Timing Challenges in Nanometer Designs
Topic Area: Circuit and interconnect analysis
Time: 1:30 PM - 3:00 PM
Location: 300
Speakers: Florentin Dartu, R&D Engineer

Summary
Technology scaling and escalation of design complexity has made assurance of timing performance under various process and environmental conditions an increasing challenge. Advances in design-time timing analysis and verification and in run-time timing failure detection are vital avenues for developing current and future nanometer designs. This session highlights recent advancements in functional and static timing analysis where novel techniques are developed to account for statistical and deterministic sources of timing variations and their interactions in an efficient and incremental manner. The session also recognizes research geared towards leveraging microarchitectural-level simulation and gate-level logic analysis for prediction and tolerance of timing violations in high performance processors.

SESSION 46: RESEARCH PAPER SESSION
Special Delivery: Challenges in Packaging
Topic Area: Physical Design
Time: 1:30 PM - 3:00 PM
Location: 306
Speakers: Chen-Feng Chang, R&D Engineer; I-Jye Lin, R&D Engineer; Chin-Fang Shen, Sr. Manager, R&D

Summary
Delivering the next generation technologies requires addressing PCB design, 3-D methodology, and most importantly, packaging. The first three papers in this session explore the collaborative design between the chip, package and board, as well as IP re-use in 3-D ICs. These methodologies deliver the promise of footprint scaling at the packaging level. Pin access can however limit the scaling at the chip level. The last paper in the session overcomes that limitation.

SESSION 51: RESEARCH PAPER SESSION
Yielding in an Uncertain World
Topic Area: Design for Manufacturability
Time: 3:30 PM - 5:30 PM
Location: 300
Speakers: Charles Chiang, Synopsys Scientist

Summary
As Moore’s Law marches into the sub-22nm regime, designers are surrounded by many uncertainties, such as lithography choices, new device architectures, and 3-D integration. These challenges have to be addressed by collective design and process integration techniques at multiple abstraction levels. EDA can play a pivotal role in bridging these disciplines. To improve yield in the uncertain world, this session covers new advancements in pattern recognition, triple patterning, EUV, novel memory, and 3-D architecture.


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